10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Table 0.1 LAN91C111 Datasheet Revision History (continued)
REVISION
LEVEL AND
DATE
NAME
SECTION/FIGURE/ENTRY
CORRECTION
Rev. 1.0
Section 8.5, "Bank 0 -
Transmit Control Register," on
page 57
Add Description for FDUPLX bit.
(07-01-02)
Rev. 1.0
Section 8.10, "Bank 0 -
Receive/Phy Control
Register," on page 61
Add Description for SPEED, DPLX, ANEG
bits.
(07-01-02)
Rev. 1.0
Section 8.21, "Bank 2 -
Interrupt Status Registers," on
page 72
Add Description for Interrupt Status and
Mask bits.
(07-01-02)
Rev. 1.0
Figure 8.2 Interrupt
Structureon page 75
Modified Interrupt Structure Figure.
Changed bit name 0 to Reserved.
Reserved bits default at 00A0.
(07-01-02)
Rev. 1.0
Chapter 9, "PHY MII
Registers ," on page 81
(07-01-02)
Rev. 1.0
Section 9.10, "Register 20.
Reserved - Structure and Bit
Definition," on page 93
(07-01-02)
Rev. 1.0
Section 10.2, "Typical Flow of
Events for Transmit (Auto
Release = 0)," on page 96
Modified Typical Flow of Event for TX.
Modified Typical Flow of Event for TX.
(07-01-02)
Rev. 1.0
Section 10.3, "Typical Flow of
Events for Transmit (Auto
Release = 1)," on page 97
(07-01-02)
SMSC LAN91C111-REV B
4
Revision 1.8 (07-13-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
