10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
7.7.4
Clock and Data Recovery
Clock Recovery - 100 Mbps
Clock recovery is done with a PLL. If there is no valid data present on the TP inputs, the PLL is locked
to the 25 MHz TX25. When valid data is detected on the TP inputs with the squelch circuit and when
the adaptive equalizer has settled, the PLL input is switched to the incoming data on the TP input.
The PLL then recovers a clock by locking onto the transitions of the incoming signal from the twisted
pair wire. The recovered dock frequency is a 25 MHz nibble dock, and that clock is outputted on the
controller interface signal RX25.
Data Recovery - 100 Mbps
Data recovery is performed by latching in data from the TP receiver with the recovered clock extracted
by the PLL. The data is then converted from a single bit stream into nibble wide data word according
to the format shown in Figure 7.2.
Clock Recovery - 10 Mbps
The clock recovery process for 10Mbps mode is identical to the 100Mbps mode except, (1) the
recovered clock frequency is 2.5 MHz nibble clock, (2) the PLL is switched from TX25 to the TP input
when the squelch indicates valid data, (3) The PLL takes up to 12 transitions (bit times) to lock onto
the preamble, so some of the preamble data symbols are lost, but the dock recovery block recovers
enough preamble symbols to pass at least 6 nibbles of preamble to the receive controller interface as
shown in Figure 7.2.
Data Recovery - 10 Mbps
The data recovery process for 10Mbps mode is identical to the 100Mbps mode. As mentioned in the
Manchester Decoder section, the data recovery process inherently performs decoding of Manchester
encoded data from the TP inputs.
7.7.5
Scrambler
100 Mbps
100BASE-TX requires scrambling to reduce the radiated emissions on the twisted pair. The
LAN91C111 scrambler takes the encoded data from the 4B5B encoder, scrambles it per the IEEE
802.3 specifications, and sends it to the TP transmitter.
10 Mbps
A scrambler is not used in 10Mbps mode.
Scrambler Bypass
The scrambler can be bypassed by setting the bypass scrambler/descrambler bit in the PHY Ml serial
port Configuration 1 register. When this bit is set, the 5B data bypasses the scrambler and goes
directly from the 4B5B encoder to the twisted pair transmitter.
7.7.6
Descrambler
100 Mbps
The LAN91C111 descrambler takes the scrambled data from the data recovery block, descrambles it
per the IEEE 802.3 specifications, aligns the data on the correct 5B word boundaries, and sends it to
the 4B5B decoder.
The algorithm for synchronization of the descrambler is the same as the algorithm outlined in the IEEE
802.3 specification. Once the descrambler is synchronized, it will maintain synchronization as long as
enough descrambled idle pattern 1's are defected within a given interval. To stay in synchronization,
the descrambler needs to detect at least 25 consecutive descrambled idle pattern 1's in a 1ms interval.
Revision 1.8 (07-13-05)
SMSC LAN91C111-REV B
DATA3S8HEET
SMSC [ SMSC CORPORATION ]
