10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
8.12
Bank 1 - Base Address Register
OFFSET
2
NAME
TYPE
SYMBOL
BAR
BASE ADDRESS
REGISTER
READ/WRITE
This register holds the I/O address decode option chosen for the LAN91C111. It is part of the EEPROM
saved setup and is not usually modified during run-time.
HIGH
A15
0
A14
0
A13
0
A9
A8
1
A7
0
A6
0
A5
BYTE
1
0
LOW
Reserved
Reserved
BYTE
0
0
0
0
0
0
0
1
A15 - A13 and A9 - A5 - These bits are compared against the I/O address on the bus to determine
the IOBASE for the LAN91C111‘s registers. The 64k I/O space is fully decoded by the LAN91C111
down to a 16 location space, therefore the unspecified address lines A4, A10, A11 and A12 must be
all zeros.
All bits in this register are loaded from the serial EEPROM. The I/O base decode defaults to 300h
(namely, the high byte defaults to 18h).
Reserved – Reserved bits.
Below chart shows the decoding of I/O Base Address 300h:
A15
A14
A13
0
A12
0
A11
0
A10
0
A9
1
A8
1
A7
0
A6
0
A5
0
A4
0
A3
0
A2
0
A1
0
A0
0
0
0
8.13
Bank 1 - Individual Address Registers
OFFSET
NAME
TYPE
SYMBOL
IAR
4
THROUG
H 9
INDIVIDUAL ADDRESS
REGISTERS
READ/WRITE
These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or
EEPROM reload. The registers can be modified by the software driver, but a STORE operation will not
modify the EEPROM Individual Address contents. Bit 0 of Individual Address 0 register corresponds
to the first bit of the address on the cable.
SMSC LAN91C111-REV B
Revision 1.8 (07-13-05)
DATA6S5HEET
SMSC [ SMSC CORPORATION ]
