10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SSD) is signaled to the controller interface. When False Carrier is detected, the MAC is notified of
false carrier and invalid received, and the bad SSD bit is set in the PHY Ml serial port Status Output
register. Once a False Carrier Event is detected, the idle pattern (two /I/I/ symbols) must be detected
before any new SSD's can be sensed.
If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern
that is neither /l/l/ nor /J/K/ symbols but does not contain at least 2 non-contiguous 0's, the data is
ignored and the receiver stays in the idle state.
10 Mbps
Since the idle period in 10 Mbps mode is defined to be the period when no data is present on the TP
inputs, then the start of packet for 10 Mbps mode is detected when valid data is detected by the TP
squelch circuit. When start of packet is detected, carrier sense signal at internal MII is asserted as
described in the Controller Interface section. Refer to the TP squelch section for 10 Mbps mode for
the algorithm for valid data detection.
7.7.11
End of Packet
100 Mbps
End of packet for 100 Mbps mode is indicated by the End of Stream Delimiter (referred to as ESD).
The ESD pattern consists of the two /T/R/ 4B5B symbols inserted after the end of the packet, as
defined in IEEE 802.3 Clause 24.
The transmit ESD is generated by the 4B5B encoder and the /T/R/ symbols are inserted by the 4B5B
encoder after the end of the transmit data packet.
The receive ESD pattern is detected by the 4B5B decoder by examining groups of 10 consecutive
code bits (two 5B words) from the descrambler during valid packet reception to determine if there is
an ESD.
If the 10 consecutive code bits from the receiver during valid packet reception consist of the /T/R/
symbols, the end of packet is detected, data reception is terminated, the MAC is notified of valid data
received, and /I/I/ symbols are substituted in place of the /T/R/ symbols.
If 10 consecutive code bits from the receiver during valid packet reception do not consist of /T/R/
symbols but consist of /I/I/ symbols instead, then the packet is considered to have been terminated
prematurely and abnormally. When this premature end of packet condition is detected, the MAC is
notified of invalid data received for the nibble associated with the first /I/ symbol. Premature end of
packet condition is also indicated by setting the bad ESD bit in the PHY Ml serial port Status Output
register.
10 Mbps
The end of packet for 10 Mbps mode is indicated with the SOI (Start of Idle) pulse. The SOI pulse is
a positive pulse containing a Manchester code violation inserted at the end of every packet.
The transmit SOI pulse is generated by the TP transmitter and inserted at the end of the data packet
after TXEN is deasserted. The transmitted SOI output pulse at the TP output is shaped by the transmit
waveshaper to meet the pulse template requirements specified in IEEE 802.3 Clause 14 and shown
in Figure 7.6.
The receive SOI pulse is detected by the TP receiver by sensing missing data transitions. Once the
SOI pulse is detected, data reception is ended and the MAC is notified of no data/invalid data received.
SMSC LAN91C111-REV B
Revision 1.8 (07-13-05)
DATA4S5HEET
SMSC [ SMSC CORPORATION ]
