10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
ETHERNET MAC
FRAME
INTERFRAME
INTERFRAME
GAP
GAP
SFD
DA
SA
LN
LN
FCS
PREAMBLE
LLC DATA
LLC DATA
100 BASE-TX DATA SYMBOLS
SFD
DA
SA
FCS ESD
SSD
IDLE
PREAMBLE
IDLE
IDLE
= [ 1 1 1 1...]
SSD = [ 1 1 0 0 0 1 0 0 0 1]
BEFORE / AFTER
4B5B ENCODING,
SCRAMBLING,
AND MLT3
= [ 1 0 1 0 ...] 62 BITS LONG
PREAMBLE
SFD = [ 1 1]
= [ DATA]
= [ 0 1 1 0 1 0 0 1 1 1]
DA, SA, LN, LLC DATA, FCS
ESD
CODING
10 BASE-T DATA SYMBOLS
SFD DA SA
LN
FCS
IDLE
PREAMBLE
LLC DATA
SOI
IDLE
IDLE
= [ NO TRANSITIONS]
= [ 1 0 1 0 ... ] 62 BITS LONG
SFD = [ 1 1]
DA, SA, LN, LLC DATA, FCS = [ DATA]
SOI = [ 1 1 ] WITH NO MID BIT TRANSITION
PREAMBLE
BEFORE / AFTER
MANCHESTER
ENCODING
Figure 7.3 TX/10BT Frame Format
On the transmit side for 100Mbps TX operation, data is received on the controller and then sent to the
4B5B encoder for formatting. The encoded data is then sent to the scrambler. The scrambled and
encoded data is then sent to the TP transmitter. The TP transmitter converts the encoded and
scrambled data into MLT-3 ternary format, reshapes the output, and drives the twisted pair cable.
On the receive side for 100Mbps TX operation, the twisted pair receiver receives incoming encoded
and scrambled MLT-3 data from the twisted pair cable, remove any high frequency noise, equalizes
the input signal to compensate for the effects of the cable, qualifies the data with a squelch algorithm,
and converts the data from MLT-3 coded twisted pair levels to internal digital levels. The output of the
twisted pair receiver then goes to a clock and data recovery block which recovers a clock from the
incoming data, uses the clock to latch in valid data into the device, and converts the data back to NRZ
format. The NRZ data is then unscrambled and decoded by the 4B5B decoder and descrambler,
respectively, and outputted to the Ethernet controller.
SMSC LAN91C111-REV B
Revision 1.8 (07-13-05)
DATA3S5HEET
SMSC [ SMSC CORPORATION ]
