10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
0ns
50ns
100ns
150ns
200ns
250n
Asynchronous Cycle - nADS=0
t2
nDATACS
Read Data
t3A
t4
valid
t6A
t1A
t5
nRD,nWR
Write Data
t5A
D0~D31 valid
Figure 14.3 Asynchronous Cycle - nADS=0
PARAMETER
MIN
10
TYP
MAX
UNITS
t1A
t2
nDATACS Setup to nRD, nWR Active
ns
ns
nDATACS Hold After nRD, nWR Inactive (Assuming nADS Tied
Low)
5
t3A
t4
nRD Low to Valid Data
nRD High to Data Invalid
Data Setup to nWR Inactive
Data Hold After nWR Inactive
nRD Strobe Width
30
15
ns
ns
ns
ns
ns
2
t5
10
5
t5A
t6A
30
Address, AEN, nBE[3:0]
nRD, nWR
Valid Address
Valid Address
t26
t13
t26A
ARDY
Data
Valid Data
Valid
Figure 14.4 Asynchronous Ready
SMSC LAN91C111-REV B
127
Revision 1.8 (07-13-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
