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LAN91C111I-NE 参数 Datasheet PDF下载

LAN91C111I-NE图片预览
型号: LAN91C111I-NE
PDF下载: 下载PDF文件 查看货源
内容描述: 10/100非PCI以太网单芯片MAC + PHY [10/100 Non-PCI Ethernet Single Chip MAC + PHY]
分类和应用: PC以太网局域网(LAN)标准
文件页数/大小: 142 页 / 1664 K
品牌: SMSC [ SMSC CORPORATION ]
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10/100 Non-PCI Ethernet Single Chip MAC + PHY  
Datasheet  
FAILED  
1
Reserved  
0
ALLOCATED PACKET NUMBER  
0
0
0
0
0
0
FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and  
only cleared when the pending allocation is satisfied. Defaults high upon reset and reset MMU  
command. For polling purposes, the ALLOC_INT in the Interrupt Status Register should be used  
because it is synchronized to the read operation. Sequence:  
1. Allocate Command  
2. Poll ALLOC_INT bit until set  
3. Read Allocation Result Register  
ALLOCATED PACKET NUMBER - Packet number associated with the last memory allocation request.  
The value is only valid if the FAILED bit is clear.  
Note: For software compatibility with future versions, the value read from the ARR after an allocation  
request is intended to be written into the PNR as is, without masking higher bits (provided  
FAILED = 0).  
8.18  
Bank 2 - FIFO Ports Register  
OFFSET  
4
NAME  
TYPE  
SYMBOL  
FIFO  
FIFO PORTS REGISTER  
READ ONLY  
This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO.  
The packet numbers to be processed by the interrupt service routines are read from this register.  
HIGH  
BYTE  
REMPTY  
Reserved  
RX FIFO PACKET NUMBER  
1
0
0
0
0
0
0
0
0
0
0
0
LOW  
TEMPTY  
Reserved  
TX FIFO PACKET NUMBER  
BYTE  
1
0
0
0
REMPTY - No receive packets queued in the RX FIFO. For polling purposes, uses the RCV_INT bit  
in the Interrupt Status Register.  
TOP OF RX FIFO PACKET NUMBER - Packet number presently at the output of the RX FIFO. Only  
valid if REMPTY is clear. The packet is removed from the RX FIFO using MMU Commands 3) or 4).  
TEMPTY - No transmit packets in completion queue. For polling purposes, uses the TX_INT bit in the  
Interrupt Status Register.  
TX FIFO PACKET NUMBER - Packet number presently at the output of the TX FIFO. Only valid if  
TEMPTY is clear. The packet is removed when a TX INT acknowledge is issued.  
Note: For software compatibility with future versions, the value read from each FIFO register is  
intended to be written into the PNR as is, without masking higher bits (provided TEMPTY and  
REMPTY = 0 respectively).  
Revision 1.8 (07-13-05)  
SMSC LAN91C111-REV B  
DATA7S0HEET