10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Chapter 14 Timing Diagrams
t2
Address, AEN, nBE[3:0]
nADS
Valid
t3
t4
Read Data
Valid
t6
t1
t5
nRD, nWR
t5A
Valid
Write Data
Figure 14.1 Asynchronous Cycle - nADS=0
PARAMETER
MIN
TYP
MAX
UNITS
t1
t2
A1-A15, AEN, nBE[3:0] Valid to nRD, nWR Active
2
5
ns
ns
A1-A15, AEN, nBE[3:0] Hold After nRD, nWR Inactive (Assuming
nADS Tied Low)
t3
nRD Low to Valid Data
nRD High to Data Invalid
Data Setup to nWR Inactive
Data Hold After nWR Inactive
nRD Strobe Width
15
15
ns
ns
ns
ns
ns
t4
2
t5
10
5
t5A
t6
15
SMSC LAN91C111-REV B
125
Revision 1.8 (07-13-05)
DATASHEET