FEAST Fast Ethernet Controller with Full Duplex Capability
PQFP/TQFP
PIN NO.
175
NAME
Asynchron-
ous Ready
SYMBOL
ARDY
BUFFER
TYPE
OD16
DESCRIPTION
Open drain output. ARDY may be used when
interfacing asynchronous buses to extend
accesses. Its rising (access completion) edge is
controlled by the XTAL1 clock and, therefore,
asynchronous to the host CPU or bus clock.
Output. This output is used when interfacing
synchronous buses and nVLBUS=0 to extend
accesses. This signal remains normally inactive,
and its falling edge indicates completion. This
signal is synchronous to the bus clock LCLK.
Input. This input is used to complete
synchronous read cycles. In EISA burst mode it
is sampled on falling LCLK edges, and
synchronous cycles are delayed until it is
sampled high.
Outputs. Only one of these interrupts is selected
to be used; the other three are tri-stated. The
selection is determined by the value of INT SEL
1-0 bits in the Configuration Register.
Output. This active low output is asserted when
AEN is low and A4-A15 decode to the
LAN91C100FD address programmed into the
high byte of the Base Address Register. nLDEV
is a combinatorial decode of unlatched address
and AEN signals.
Input. Used in asynchronous bus interfaces.
Input. Used in asynchronous bus interfaces.
Input. When nDATACS is low, the Data Path
can be accessed regardless of the values of
AEN, A1-A15 and the content of the BANK
SELECT Register. nDATACS provides an
interface for bursting to and from the
LAN91C100FD 32 bits at a time.
Output. 4
µsec
clock used to shift data in and
out of the serial EEPROM.
Output. Serial EEPROM chip select. Used for
selection and command framing of the serial
EEPROM.
Output. Connected to the DI input of the serial
EEPROM.
Input. Connected to the DO output of the serial
EEPROM.
Input. External switches can be connected to
these lines to select between predefined
EEPROM configurations.
Input. Enables (when high or open)
LAN91C100FD accesses to the serial EEPROM.
Must be grounded if no EEPROM is connected
to the LAN91C100FD.
106
nSynchron
-
ous Ready
nReady
Return
nSRDY
O16
109
nRDYRTN
I
176,
187-189
108
Interrupt
INTR0-
INTR3
O24
nLocal
Device
nLDEV
O16
177
178
190
nRead
Strobe
nWrite
Strobe
nData
Path Chip
Select
nRD
nWR
nDATACS
IS
IS
I with
pullup
54
55
EEPROM
Clock
EEPROM
Select
EEPROM
Data Out
EEPROM
Data In
I/O Base
EESK
EECS
O4
O4
52
53
13, 15, 16
EEDO
EEDI
IOS0-
IOS2
ENEEP
O4
I with
pulldown
I with
pullup
I with
pullup
51
Enable
EEPROM
Rev. 10/14/2002
Page 8
SMSC DS – LAN91C100FD Rev. D
PRELIMINARY
SMSC [ SMSC CORPORATION ]
