TXEMPTY INTR
Write Acknowledge Reg. with
TXEMPTY Bit Set
Read TXEMPTY & TX INTR
TXEMPTY = 1
&
TXINT = 0
TXEMPTY = 0
&
TXINT = 0
TXEMPTY = X
&
TXINT = 1
(Everything went through
successfully)
(Waiting for Completion)
(Transmission Failed)
Read Pkt. # Register & Save
Write Address Pointer
Register
Read Status Word from RAM
Update Statistics
Update Variables
Issue "Release" Command
Acknowledge TXINTR
Re-Enable TXENA
Restore Packet Number
Return to ISR
60