High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 2.5 System and Power Signals (continued)
PIN
NO.
BUFFER NUM
NAME
Core Voltage
SYMBOL
DESCRIPTION
TYPE
PINS
3,65
VDD_CORE
P
2
1.8 V from internal core regulator.
Both pins must be connected
together externally and then tied to a
10uF 0.1-Ohm ESR capacitor, in
parallel with a 0.01uF capacitor to
Ground next to each pin. See
Note 2.1
Decoupling
1,66
7
Core Ground
PLL Power
GND_CORE
VDD_PLL
P
P
2
1
Ground for internal digital logic
1.8V Power from the internal PLL
regulator. This external pin must be
connected to a 10uF 0.1-Ohm ESR
capacitor, in parallel with a 0.01uF
capacitor to Ground. See Note 2.1
4
8
PLL Ground
VSS_PLL
VDD_REF
P
P
1
1
GND for the PLL
Reference Power
Connected to 3.3v power and used
as the reference voltage for the
internal PLL
11
Reference Ground
VSS_REF
P
1
Ground for internal PLL reference
voltage
Note 2.1 Please refer to the SMSC application note AN 12.5 titled “Designing with the LAN9118 -
Getting Started”. It is also important to note that this application note applies to the whole
SMSC LAN9118 family of Ethernet controllers. However, subtle differences may apply.
2.1
Buffer Types
Table 2.6 Buffer Types
TYPE
DESCRIPTION
Input pin
I
IS
Schmitt triggered Input
Output with 12mA sink and 12mA source
Open-drain output with 12mA sink
I/O with 8mA symmetrical drive
Open-drain output with 8mA sink
Output 8mA symmetrical drive
50uA (typical) internal pull-up
50uA (typical) internal pull-down
Analog input
O12
OD12
IO8
OD8
O8
PU
PD
AI
Analog output
AO
Revision 1.3 (05-31-07)
SMSC LAN9118
DATA2S0HEET
SMSC [ SMSC CORPORATION ]
