High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 2.1 Host Bus Interface Signals
BUFFER
TYPE
#
PIN NO.
NAME
SYMBOL
PINS
DESCRIPTION
Bi-directional data port.
21-26,29-
33,36-40
Host Data High
D[31:16]
I/O8 (PD)
16
16
Note that Pull-down’s are disabled in
32 bit mode.
43-46,49-
53,56-59,62-
64
Host Data Low
D[15:0]
I/O8
Bi-directional data port.
12-18
Host Address
Read Strobe
Write Strobe
A[7:1]
nRD
IS
IS
IS
7
1
1
7-bit Address Port. Used to select
Internal CSR’s and TX and RX FIFOs.
92
Active low strobe to indicate a read
cycle.
93
nWR
Active low strobe to indicate a write
cycle. This signal, qualified with nCS, is
also used to wakeup the LAN9118
when it is in a reduced power state.
94
Chip Select
nCS
IS
1
Active low signal used to qualify read
and write operations. This signal
qualified with nWR is also used to
wakeup the LAN9118 when it is in a
reduced power state.
72
76
Interrupt
Request
IRQ
O8/OD8
IS
1
1
Programmable Interrupt request.
Programmable polarity, source and
buffer types.
FIFO Select
FIFO_SEL
When driven high all accesses to the
LAN9118 are to the RX or TX Data
FIFOs. In this mode, the A[7:3] upper
address inputs are ignored.
Table 2.2 Default Ethernet Settings
DEFAULT ETHERNET SETTINGS
DUPLEX
SPEED_SEL
SPEED
10MBPS
100MBPS
AUTO NEG.
DISABLED
ENABLED
0
1
HALF-DUPLEX
HALF-DUPLEX
SMSC LAN9118
Revision 1.3 (05-31-07)
DATA1S5HEET
SMSC [ SMSC CORPORATION ]
