High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 2.6 MII Interface Signals
PIN
NO.
BUFFER
TYPE
NUM
PINS
NAME
SYMBOL
DESCRIPTION
40
Transmit Clock:
TX_CLK
I (PD)
1
Transmit Clock: 25MHz in 100Base-
TX mode. 2.5MHz in 10Base-T
mode.
36,37,
38, 39
Transmit Data [3:0]
Transmit Enable
TXD[3:0]
TX_EN
O8 (PD)
4
Transmit Data 3-0: Data bits that are
accepted by the PHY for
transmission.
When the internal PHY is selected,
these signals are driven low (0).
21
O8 (PD)
1
Transmit Enable: Indicates that valid
data is presented on the TXD[3:0]
signals, for transmission.
When the internal PHY is selected,
this signal is driven low (0).
26
25
Receive Clock
Receive Error
RX_CLK
RX_ER
I (PD)
I (PD)
1
1
Receive Clock: 25MHz in 100Base-
TX mode. 2.5MHz in 10Base-T
mode.
Receive Error: Asserted bt the PHY
to indicate that an error was detected
somewhere in the frame presently
being transferred from the PHY.
33
Collision Detect:
Receive Data[3:0]
Carrier Sense
COL/
I (PD)
I (PD)
1
1
MII Collision Detect: Asserted by the
PHY to indicate detection of collision
condition.
24,23,
22, 75
RXD[3:0]
Receive Data 3-0: Data bits that are
sent from the PHY to the Ethernet
MAC.
32
29
CRS
I (PD)
I (PD)
1
1
Carrier Sense: Indicates detection of
carrier.
Receive Data
Valid:
RX_DV
Receive Data Valid: Indicates that
recovered and decoded data nibbles
are being presented by the PHY on
RXD[3:0].
30
Management Data
IO/External PHY
Detect
MDIO
I/O8
(PD)
1
Management Data IO: When
SMI_SEL = 1, this pin is the MII SMI
serial IO bus pin.
(EXT_PHY_DET)
External PHY Detect: This pin also
functions as a strap input, which can
be used to indicate the presence of
an external PHY.
See Note 2.2.
Note:
See Section 5.3.9,
"HW_CFG—Hardware
Configuration Register" for
more information on
SMI_SEL and
EXT_PHY_DET
Revision 1.1 (05-17-05)
SMSC LAN9117
DATA2S0HEET
SMSC [ SMSC CORPORATION ]
