Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.4.5
HASHL—Multicast Hash Table Low Register
Offset:
5
Attribute:
Size:
R/W
Default Value:
00000000h
32 bits
This register defines the lower 32-bits of the Multicast Hash Table. Please refer to Table 5.4.4,
"HASHH—Multicast Hash Table High Register" for further details.
BITS
31-0
DESCRIPTION
Lower 32 bits of the 64-bit Hash Table
5.4.6
MII_ACC—MII Access Register
Offset:
6
Attribute:
Size:
R/W
Default Value:
00000000h
32 bits
This register is used to control the Management cycles to the PHY.
BITS
31-16
15-11
10-6
5-2
DESCRIPTION
Reserved
PHY Address: For every access to this register, this field must be set to 00001b.
MII Register Index (MIIRINDA): These bits select the desired MII register in the PHY.
Reserved
1
MII Write (MIIWnR): Setting this bit tells the PHY that this will be a write operation using the MII data
register. If this bit is not set, this will be a read operation, packing the data in the MII data register.
0
MII Busy (MIIBZY): This bit must be polled to determine when the MII register accesss is complete.
This bit must read a logical 0 before writing to this register and MII data register.
The LAN driver software must set (1) this bit in order for the LAN9116 to read or write any of the MII
PHY registers.
During a MII register access, this bit will be set, signifying a read or write access is in progress. The
MII data register must be kept valid until the MAC clears this bit during a PHY write operation. The
MII data register is invalid until the MAC has cleared this bit during a PHY read operation.
SMSC LAN9116
Revision 1.1 (05-17-05)
DATA9S7HEET
SMSC [ SMSC CORPORATION ]
