Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.4.7
MII_DATA—MII Data Register
Offset:
7
Attribute:
Size:
R/W
Default Value:
00000000h
32 bits
This register contains either the data to be written to the PHY register specified in the MII Access
Register, or the read data from the PHY register whose index is specified in the MII Access Register.
BITS
DESCRIPTION
31-16
15-0
Reserved
MII Data. This contains the 16-bit value read from the PHY read operation or the 16-bit data value to
be written to the PHY before an MII write operation.
5.4.8
FLOW—Flow Control Register
Offset:
8
Attribute:
Size:
R/W
Default Value:
00000000h
32 bits
This register controls the generation and reception of the Control (Pause command) frames by the
MAC’s flow control block. The control frame fields are selected as specified in the 802.3x Specification
and the Pause-Time value from this register is used in the “Pause Time” field of the control frame. In
full-duplex mode the FCBSY bit is set until the control frame is transferred onto the cable. In half-
duplex mode FCBSY is set while back pressure is being asserted. The host has to make sure that the
Busy bit is cleared before writing the register. The Pass Control Frame bit (FCPASS) does not affect
the sending of the frames, including Control Frames, to the Application Interface. The Flow Control
Enable (FCEN) bit enables the receive portion of the Flow Control block.
This register is used in conjunction with the AFC_CFG register in the Slave CSRs to configure flow
control. Software flow control is initiated using the AFC_CFG register.
Note: The LAN9116 will not transmit pause frames or assert back pressure if the transmitter is
disabled.
BITS
DESCRIPTION
31-16
Pause Time (FCPT). This field indicates the value to be used in the PAUSE TIME field in the control
frame. This field must be initialized before full-duplex automatic flow control is enabled.
15-3
Reserved
Revision 1.1 (05-17-05)
SMSC LAN9116
DATA9S8HEET
SMSC [ SMSC CORPORATION ]
