Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
3.6
Interrupt Management
The device management interface supports an interrupt capability that is not a part of the IEEE 802.3
specification. This interrupt capability generates an active low asynchronous interrupt signal on the
nINT output whenever certain events are detected as setup by the Interrupt Mask Register.
The device’s interrupt system provides two modes, a Primary Interrupt mode and an Alternative
interrupt mode. Both systems will assert the nINT pin low when the corresponding mask bit is set.
These modes differ only in how they de-assert the nINT interrupt output. These modes are detailed in
the following subsections.
Note: The Primary interrupt mode is the default interrupt mode after a power-up or hard reset. The
Alternative interrupt mode requires setup after a power-up or hard reset.
3.6.1
Primary Interrupt System
The Primary interrupt system is the default interrupt mode (ALTINT bit of the Mode Control/Status
Register is “0”). The Primary interrupt system is always selected after power-up or hard reset. In this
mode, to set an interrupt, set the corresponding mask bit in the Interrupt Mask Register (see Table 3.2).
Then when the event to assert nINT is true, the nINT output will be asserted. When the corresponding
event to deassert nINT is true, then the nINT will be de-asserted.
Table 3.2 Interrupt Management Table
INTERRUPT SOURCE
FLAG
EVENT TO
ASSERT nINT
EVENT TO
DE-ASSERT nINT
MASK
INTERRUPT SOURCE
30.7
29.7
ENERGYON
17.1
ENERGYON
Rising 17.1
(Note 3.1)
Falling 17.1 or
Reading register 29
30.6
30.5
29.6
29.5
Auto-Negotiation
complete
1.5
1.4
Auto-Negotiate
Complete
Rising 1.5
Falling 1.5 or
Reading register 29
Remote Fault
Detected
Remote Fault
Rising 1.4
Falling 1.4, or
Reading register 1 or
Reading register 29
30.4
30.3
30.2
29.4
29.3
29.2
Link Down
1.2
Link Status
Falling 1.2
Rising 5.14
Rising 6.4
Reading register 1 or
Reading register 29
Auto-Negotiation
LP Acknowledge
5.14
6.4
Acknowledge
Falling 5.14 or
Read register 29
Parallel Detection
Fault
Parallel
Detection Fault
Falling 6.4 or
Reading register 6, or
Reading register 29
or
Re-Auto Negotiate or
Link down
30.1
29.1
Auto-Negotiation
Page Received
6.1
Page Received
Rising 6.1
Falling of 6.1 or
Reading register 6, or
Reading register 29
Re-Auto Negotiate, or
Link Down.
Note 3.1 If the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high,
nINT will assert for 256 ms, approximately one second after ENERGYON goes low when
the Cable is unplugged. To prevent an unexpected assertion of nINT, the ENERGYON
interrupt mask should always be cleared as part of the ENERGYON interrupt service
routine.
SMSC LAN8720A/LAN8720Ai
29
Revision 1.4 (08-23-12)
DATASHEET
SMSC [ SMSC CORPORATION ]
