®
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR Technology
Datasheet
3.7
Configuration Straps
Configuration straps allow various features of the device to be automatically configured to user defined
values. Configuration straps are latched upon Power-On Reset (POR) and pin reset (nRST).
Configuration straps include internal resistors in order to prevent the signal from floating when
unconnected. If a particular configuration strap is connected to a load, an external pull-up or pull-down
resistor should be used to augment the internal resistor to ensure that it reaches the required voltage
level prior to latching. The internal resistor can also be overridden by the addition of an external
resistor.
Note: The system designer must guarantee that configuration strap pins meet the timing
requirements specified in Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on
page 72. If configuration strap pins are not at the correct voltage level prior to being latched,
the device may capture incorrect strap values.
Note: When externally pulling configuration straps high, the strap should be tied to VDDIO, except
for REGOFF and nINTSEL which should be tied to VDD2A.
3.7.1
PHYAD[2:0]: PHY Address Configuration
The PHYAD[2:0] configuration straps are driven high or low to give each PHY a unique address. This
address is latched into an internal register at the end of a hardware reset (default = 000b). In a multi-
transceiver application (such as a repeater), the controller is able to manage each transceiver via the
unique address. Each transceiver checks each management data frame for a matching address in the
relevant bits. When a match is recognized, the transceiver responds to that particular frame. The PHY
address is also used to seed the scrambler. In a multi-transceiver application, this ensures that the
scramblers are out of synchronization and disperses the electromagnetic radiation across the
frequency spectrum.
The device’s SMI address may be configured using hardware configuration to any value between 0
and 7. The user can configure the PHY address using Software Configuration if an address greater
than 7 is required. The PHY address can be written (after SMI communication at some address is
established) using the PHYAD bits of the Special Modes Register. The PHYAD[2:0] configuration straps
are multiplexed with other signals as shown in Table 3.5.
Table 3.5 Pin Names for Address Bits
ADDRESS BIT
PIN NAME
PHYAD[0]
PHYAD[1]
PHYAD[2]
RXER/RXD4/PHYAD0
RXCLK/PHYAD1
RXD3/PHYAD2
3.7.2
MODE[2:0]: Mode Configuration
The MODE[2:0] configuration straps control the configuration of the 10/100 digital block. When the
nRST pin is deasserted, the register bit values are loaded according to the MODE[2:0] configuration
straps. The 10/100 digital block is then configured by the register bit values. When a soft reset occurs
via the Soft Reset bit of the Basic Control Register, the configuration of the 10/100 digital block is
controlled by the register bit values and the MODE[2:0] configuration straps have no affect.
The device’s mode may be configured using the hardware configuration straps as summarized in
Table 3.6. The user may configure the transceiver mode by writing the SMI registers.
Revision 1.4 (08-23-12)
36
SMSC LAN8710A/LAN8710Ai
DATASHEET
SMSC [ SMSC CORPORATION ]
