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LAN8700IC-AEZG 参数 Datasheet PDF下载

LAN8700IC-AEZG图片预览
型号: LAN8700IC-AEZG
PDF下载: 下载PDF文件 查看货源
内容描述: [LAN Controller, 4 Channel(s), 12.5MBps, CMOS, 6 X 6 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, QFN-36]
分类和应用: 通信时钟局域网数据传输外围集成电路
文件页数/大小: 83 页 / 687 K
品牌: SMSC [ SMSC CORPORATION ]
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±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR® Technology in a Small Footprint  
Datasheet  
Table 5.36 Register 6 - Auto Negotiation Expansion  
ADDRESS  
NAME  
DESCRIPTION  
MODE DEFAULT  
6.15:5  
6.4  
Reserved  
RO  
0
0
Parallel Detection  
Fault  
1 = fault detected by parallel detection logic  
0 = no fault detected by parallel detection logic  
RO/  
LH  
6.3  
6.2  
6.1  
6.0  
Link Partner Next  
Page Able  
1 = link partner has next page ability  
RO  
0
0
0
0
0 = link partner does not have next page ability  
Next Page Able  
1 = local device has next page ability  
0 = local device does not have next page ability  
RO  
Page Received  
1 = new page received  
0 = new page not yet received  
RO/  
LH  
Link Partner Auto- 1 = link partner has auto-negotiation ability  
Negotiation Able  
RO  
0 = link partner does not have auto-negotiation ability  
Table 5.37 Register 16 - Silicon Revision  
DESCRIPTION  
ADDRESS  
NAME  
MODE DEFAULT  
16.15:10  
16.9:6  
Reserved  
Silicon Revision  
Reserved  
RO  
RO  
RO  
0
0001  
0
Four-bit silicon revision identifier.  
16.5:0  
Table 5.38 Register 17 - Mode Control/Status  
ADDRESS  
NAME  
DESCRIPTION  
MODE DEFAULT  
17.15:14  
17.13  
Reserved  
Write as 0; ignore on read.  
RW  
RW  
0
0
EDPWRDOWN  
Enable the Energy Detect Power-Down mode:  
0 = Energy Detect Power-Down is disabled  
1 = Energy Detect Power-Down is enabled  
17.12  
17.11  
Reserved  
Write as 0, ignore on read  
RW  
RW  
0
0
LOWSQEN  
The Low_Squelch signal is equal to LOWSQEN AND  
EDPWRDOWN.  
Low_Squelch = 1 implies a lower threshold  
(more sensitive).  
Low_Squelch = 0 implies a higher threshold  
(less sensitive).  
17.10  
17.9  
MDPREBP  
Management Data Preamble Bypass:  
0 – detect SMI packets with Preamble  
1 – detect SMI packets without preamble  
RW  
RW  
0
0
FARLOOPBACK  
Force the module to the FAR Loop Back mode, i.e. all  
the received packets are sent back simultaneously (in  
100Base-TX only). This bit is only active in RMII  
mode. In this mode the user needs to supply a 50MHz  
clock to the PHY. This mode works even if MII Isolate  
(0.10) is set.  
SMSC LAN8700/LAN8700i  
Revision 2.3 (04-12-11)  
DATA4S5HEET