±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR® Technology in a Small Footprint
Datasheet
Phy Address = 1
Phy Address = 0
LEDoutput=activehigh
LED output= activelow
VDD
LED1-LED4
~10Kohms
~270ohms
~270ohms
LED1-LED4
Figure 4.5 PHY Address Strapping on LED’s
4.12
Variable Voltage I/O
The Digital I/O pins on the LAN8700/LAN8700i are variable voltage to take advantage of low power
savings from shrinking technologies. These pins can operate from a low I/O voltage of +1.8V-10% up
to +3.3V+10%. Due to this low voltage feature addition, the system designer needs to take
consideration as for two aspects of their design. Boot strapping configuration and I/O voltage stability.
4.12.1
Boot Strapping Configuration
Due to a lower I/O voltage, a lower strapping resistor needs to be used to ensure the strapped
configuration is latched into the PHY device at power-on reset.
.
Table 4.3 Boot Strapping Configuration Resistors
I/O voltage
3.0 to 3.6
2.0 to 3.0
1.6 to 2.0
Pull-up/Pull-down Resistor
10k ohm resistor
7.5k ohm resistor
5k ohm resistor
4.12.2
I/O Voltage Stability
The I/O voltage the System Designer applies on VDDIO needs to maintain its value with a tolerance
of ± 10%. Varying the voltage up or down, after the PHY has completed power-on reset can cause
errors in the PHY operation.
4.13
PHY Management Control
The Management Control module includes 3 blocks:
Serial Management Interface (SMI)
Management Registers Set
Interrupt
SMSC LAN8700/LAN8700i
Revision 2.3 (04-12-11)
DATA3S3HEET
SMSC [ SMSC CORPORATION ]
