±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR® Technology in a Small Footprint
Datasheet
When the +1.8V internal regulator is disabled, a 0.1uF capacitor must be added at the VDD_CORE
pin and placed close to the PHY to decouple the external power supply.
4.9.2
Enable the Internal +1.8V Regulator
The 1.8V for VDD_CORE is supplied by the on-chip regulator unless the PHY is configured for
regulator off mode using the RX_CLK/REGOFF pin as described in Section 4.9.1. By default, the
internal +1.8V regulator is enabled when the RXCLK/REGOFF pin is floating. As shown in Table 7.11,
an internal pull-down resistor straps the regulator on if the RXCLK/REGOFF pin is floating.
During VDDIO and VDDA power-on, if the RXCLK/REGOFF pin is sampled below VIL, then the internal
+1.8V regulator will turn on and operate with power from the VDD33 pin.
When using the internal linear regulator, a 4.7uF bypass capacitor with ESR < 1ohm and a 0.1uF
capacitor must always be added to VDD_CORE and placed close to the PHY to ensure stability of the
internal regulator.
4.10
4.11
nINT/TX_ER/TXD4 Strapping
The nINT, TX_ER, and TXD4 functions share a common pin. There are two functional modes for this
pin, the TX_ER/TXD4 mode and nINT (interrupt) mode. The RXD3/nINTSEL pin is used to select one
of these two functional modes.
The RXD3/nINTSEL pin is latched on the rising edge of the nRST. The system designer must float the
nINTSEL pin to put the nINT/TX_ER/TXD4 pin into nINT mode or pull-low to VSS with an external
resistor (see Table 4.3, “Boot Strapping Configuration Resistors,” on page 33) to set the device in
TX_ER/TXD4 mode. The default setting is to float the pin high for nINT mode.
PHY Address Strapping and LED Output Polarity Selection
The PHY ADDRESS bits are latched on the rising edge of the internal reset (nRESET). The 5-bit
address word[0:4] is input on the PHYAD[0:4] pins. The default setting is all high 5'b1_1111.
The address lines are strapped as defined in the diagram below. The LED outputs will automatically
change polarity based on the presence of an external pull-down resistor. If the LED pin is pulled high
(by an internal 100K pull-up resistor) to select a logical high PHY address, then the LED output will
be active low. If the LED pin is pulled low (by an external pull-down resistor (see Table 4.3, “Boot
Strapping Configuration Resistors,” on page 33) to select a logical low PHY address, the LED output
will then be an active high output.
To set the PHY address on the LED pins without LEDs or on the CRS pin, float the pin to set the
address high or pull-down the pin with an external resistor (see Table 4.3, “Boot Strapping
Configuration Resistors,” on page 33) to GND to set the address low. See Figure 4.5, "PHY Address
Strapping on LED’s":
Revision 2.3 (04-12-11)
SMSC LAN8700/LAN8700i
DATA3S2HEET
SMSC [ SMSC CORPORATION ]
