±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR® Technology in a Small Footprint
Datasheet
Chapter 4 Architecture Details
4.1
Top Level Functional Architecture
Functionally, the PHY can be divided into the following sections:
100Base-TX transmit and receive
10Base-T transmit and receive
MII or RMII interface to the controller
Auto-negotiation to automatically determine the best speed and duplex possible
Management Control to read status registers and write control registers
TX_CLK
(for M II only)
100M
PLL
MAC
Ext Ref_CLK (for RMII only)
MII 25 Mhz by 4 bits
4B/5B
Encoder
Scram bler
and PISO
25MHz
by 4 bits
25M Hz by
5 bits
or
MII
RM II 50Mhz by 2 bits
125 Mbps Serial
NRZI
Converter
MLT-3
Converter
Tx
Driver
NRZI
M LT-3
MLT-3
Magnetics
MLT-3
MLT-3
RJ45
CAT-5
Figure 4.1 100Base-TX Data Path
4.2
100Base-TX Transmit
The data path of the 100Base-TX is shown in Figure 4.1. Each major block is explained below.
4.2.1
100M Transmit Data Across the MII/RMII Interface
For MII, the MAC controller drives the transmit data onto the TXD bus and asserts TX_EN to indicate
valid data. The data is latched by the PHY’s MII block on the rising edge of TX_CLK. The data is in
the form of 4-bit wide 25MHz data.
The MAC controller drives the transmit data onto the TXD bus and asserts TX_EN to indicate valid
data. The data is latched by the PHY’s MII block on the rising edge of REF_CLK. The data is in the
form of 2-bit wide 50MHz data.
4.2.2
4B/5B Encoding
The transmit data passes from the MII block to the 4B/5B encoder. This block encodes the data from
4-bit nibbles to 5-bit symbols (known as “code-groups”) according to Table 4.1. Each 4-bit data-nibble
is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for
control information or are not valid.
SMSC LAN8700/LAN8700i
Revision 2.3 (04-12-11)
DATA1S9HEET
SMSC [ SMSC CORPORATION ]
