PCI INTERFACE
BIG/LITTLE ENDIAN SUPPORT
The transmit and receive DMA controllers
access the PCI bus through the PCI bus
In order to run in Big Endian machines, the
LAN83C171 can be programmed to swap bytes
on the data bus in certain circumstances. In
Macintosh Power PC computers the bridge
between the Big Endian processor data bus and
the Little Endian PCI bus swaps the order of the
bytes on the data bus (during data phase only -
addresses are never modified). This means that
byte size quantities transferred over the data
bus always end up in the correct location for
their given address, but when 32 bit (dword)
quantities are transferred they end up with their
bytes reversed.
Master/Slave Interface logic.
This block is
responsible for requesting the PCI bus and
conducting all bus master operations according
to the PCI bus protocol (including parity
generation and error detection). This block is
also responsible for responding to all slave
operations according to PCI bus protocol
(including
address
recognition,
parity
generation, and error detection).
TRANSMIT/RECEIVE ARBITRATION FOR PCI
BUS
When programmed into Big Endian mode, the
LAN83C171 automatically swaps the data bytes
internally when reading or writing descriptor
Another major function of the PCI Bus
Master/Slave Interface block is to arbitrate
between the transmit and receive DMA
controllers for access to the PCI bus.
tables or fragment lists.
This allows the
software driver to treat the descriptor and
fragment list entries as 32 bit quantities and not
worry about byte ordering.
SYSTEM ERRORS
In order to comply with the PCI specification, the
LAN83C171 does not swap the data bytes on
reads or writes to the configuration or control
register space. The software driver is
responsible for interpreting correctly the bytes
when performing 32 bit register read or writes
on a Big Endian machine.
There are four types of PCI bus errors that are
considered fatal by the LAN83C171. They are
Master Abort, Target Abort, Address Parity
Error, and Data Parity Error (see interrupt status
register for details). If any of these errors
occurs, the LAN83C171 will set the appropriate
interrupt and immediately discontinue all DMA
activity. The receiver will automatically be taken
offline and any transmissions in progress will be
completed without a valid CRC appended (in
case transmit data was corrupted). Normal
operation may only be resumed by resetting the
LAN83C171 with the soft reset bit. The software
driver should make sure the transmitter and
receiver have returned to their idle states (by
polling the TXIDLE and RXIDLE bits in the
interrupt status register) before resetting the
device.
When reading or writing Ethernet packet data,
the LAN83C171 does not perform any byte
swapping internally because the data on the PCI
bus is already in the correct order.
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SMSC [ SMSC CORPORATION ]
