High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
The minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400
ns. These modest timing requirements allow this interface to be easily driven by the I/O port of a
microcontroller.
The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing
of the data is shown in Figure 4.4 and Figure 4.5.
The timing relationships of the MDIO signals are further described in Section 6.1, "Serial
Management Interface (SMI) Timing," on page 47.
Read Cycle
MDC
MDI0
...
...
D1
D15 D14
D0
32 1's
0
1
1
0
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
Start of
Frame
OP
Code
Turn
Preamble
PHY Address
Register Address
Data
Around
Data To Phy
Data From Phy
Figure 4.4 MDIO Timing and Frame Structure - READ Cycle
Write Cycle
MDC
...
...
D15 D14
D1
D0
32 1's
0
1
0
1
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
PHY Address Register Address
MDIO
Start of
Frame
OP
Code
Turn
Preamble
Data
Around
Data To Phy
Figure 4.5 MDIO Timing and Frame Structure - WRITE Cycle
SMSC LAN83C185
Rev. 0.6 (12-12-03)
DATA2S1HEET
SMSC [ SMSC CORPORATION ]
