USB2.0 PHY IC
Chapter 2 Functional Block Diagram
VDD3.3
PWR
CONTROL
TX
LOGIC
TX State
Machine
DATABUS16_8
RESET
SUSPENDN
XCVRSELECT
TERMSELECT
OPMODE[1:0]
VDD1.8
Parallel to
Serial
Conversion
Bit Stuff
NRZI
Encode
XO
PLL and
XTAL OSC
HS_DRIVE_ENABLE
HS_CS_ENABLE
HS TX
XI
System
Clocking
TX
RPU_EN
1.5kΩ
VPO
VMO
OEB
HS_DATA
FS TX
DP
LINESTATE[1:0]
CLKOUT
RX
DM
UTMI Interface
RX
LOGIC
RX State
Machine
Serial to
Parallel
Conversion
Bit Unstuff
VP
VM
FS SE+
DATA[15:0] *
TXVALID
TXREADY
VALIDH
FS SE-
Clock
Recovery Unit
Clock
and
Data
Recovery
Elasticity
Buffer
FS RX
MUX
RXVALID
RXACTIVE
RXERROR
NRZI
Decode
HS RX
BIASING
Bandgap Voltage Reference
Current Reference
HS SQ
Figure 2.1 Block Diagram
Note:
See
for a description of the digital interface.
SMSC GT3200, SMSC USB3250
RBIAS
DATASHEET
2
Revision 1.3 (10-05-04)
SMSC [ SMSC CORPORATION ]
