POWER FUNCTIONALITY
The FDC37M81x has two power planes: VCC
must be at its full minimum potential at least 10
ms before Vcc begins a power-on cycle. When
VTR and Vcc are fully powered, the potential
difference between the two supplies must not
exceed 500mV.
and VTR.
VCC Power
The FDC37M81x is a 5 Volt part. The VCC
supply is 5 Volts (nominal). See the Operational
Description sections and the Maximum Current
Values subsection.
Internal PWRGOOD
An internal PWRGOOD logical control is
included to minimize the effects of pin-state
uncertainty in the host interface as Vcc cycles on
and off. When the internal PWRGOOD signal is
“1” (active), Vcc is > 3.7V, and the FDC37M81x
host interface is active. When the internal
PWRGOOD signal is “0” (inactive), Vcc is £
3.7V, and the FDC37M81x host interface is
inactive; that is, ISA bus reads and writes will
not be decoded.
VTR SUPPORT
The FDC37M81x requires a 25 mA max trickle
supply (VTR) to provide sleep current for the
programmable wake-up events in the PME
interface when VCC is removed.
If the
FDC37M81x is not intended to provide wake-up
capabilities on standby current, VTR can be
connected to VCC
.
VTR powers the PME
configuration registers, and the PME interface.
The VTR pin generates a VTR Power-on-Reset
signal to initialize these components.
The FDC37M81x device pins nIO_PME, KDAT,
MDAT, IRRX, nRI1, nRI2 and RXD2 are part of
the PME interface and remain active when the
internal PWRGOOD signal has gone inactive,
provided VTR is powered.
Note: If VTR is to be used for programmable
wake-up events when VCC is removed, VTR
FDC37M81x PLL CONTROLS AND SELECTS
PLL CONTROL
PME POWER
INTERNAL
(CR24.1)
(CR22.7)
PWRGOOD
DESCRIPTION
14 MHz PLL Powered Down
Reserved
14MHz PLL Powered, Selected.
Reserved
1
0
0
0
0
X
0
0
1
1
X
0
1
0
1
Reserved
12
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