Enhanced Super I/O Controller with Fast IR
Datasheet
Figure 21.7 - Reset Timing.........................................................................................................................................151
Figure 21.8 - DMA Timing (Single Transfer Mode).....................................................................................................152
Figure 21.9 - DMA Timing (Burst Transfer Mode) ......................................................................................................153
Figure 21.10 - Disk Drive Timing (At Mode Only).......................................................................................................154
Figure 21.11 - Serial Port Timing ...............................................................................................................................155
Figure 21.12 - Parallel Port Timing.............................................................................................................................156
Figure 21.13 - EPP 1.9 Data or Address Write Cycle.................................................................................................157
Figure 21.14 - EPP 1.9 Data or Address Read Cycle ................................................................................................159
Figure 21.15 - EPP 1.7 Data or Address Write Cycle.................................................................................................161
Figure 21.16 - EPP 1.7 Data or Address Read Cycle ................................................................................................163
Figure 22.1 - Parallel Port FIFO Timing.......................................................................................................................165
Figure 22.2 - ECP Parallel Port Forward Timing..........................................................................................................166
Figure 22.3 - ECP Parallel Port Reverse Timing .........................................................................................................167
Figure 22.4 - IrDA Receive Timing .............................................................................................................................168
Figure 22.5 - IrDA Transmit Timing ............................................................................................................................169
Figure 22.6 - Amplitude Shift Keyed IR Receive Timing ............................................................................................170
Figure 22.7 - Amplitude Shift Keyed IR Transmit Timing ...........................................................................................171
Figure 23.1 - 100 Pin QFP Package Outline and Parameters .....................................................................................172
Figure 23.2 - 100 Pin TQFP Package Outline, 14X14X1.4 Body, 2 MM Footprint .......................................................173
List of Tables
Table 5.1 - Super I/O Block Addresses .........................................................................................................................17
Table 6.1 - Status, Data and Control Registers .............................................................................................................18
Table 6.2 - Drive Activation Values ...............................................................................................................................24
Table 6.3 - Tape Select Bits..........................................................................................................................................24
Table 6.4 - Internal 2 Drive Decode - Normal ................................................................................................................24
Table 6.5 - Internal 2 Drive Decode - Drives 0 and 1 Swapped .....................................................................................25
Table 6.6 - Media ID1...................................................................................................................................................26
Table 6.7 - Media ID0...................................................................................................................................................26
Table 6.8 - Drive Type ID..............................................................................................................................................26
Table 6.9 - Precompensation Delays ............................................................................................................................27
Table 6.10 - Data Rates ...............................................................................................................................................28
Table 6.11 - DRVDEN Mapping....................................................................................................................................28
Table 6.12 - Default Precompensation Delays ..............................................................................................................28
Table 6.14 -
FIFO Service Delay
....................................................................................................................................30
Table 6.15 - Status Register 0 ......................................................................................................................................34
Table 6.16 - Status Register 1 ......................................................................................................................................34
Table 6.17 - Status Register 2 ......................................................................................................................................35
Table 6.18 - Status Register 3 ......................................................................................................................................35
Table 7.1 - Description of Command Symbols ..............................................................................................................40
Table 8.1 - Sector Sizes ...............................................................................................................................................50
Table 8.2 - Effects of MT and N Bits .............................................................................................................................50
Table 8.3 - Skip Bit vs Read Data Command ................................................................................................................51
Table 8.4 - Skip Bit vs. Read Deleted Data Command ..................................................................................................51
Table 8.5 - Result Phase Table.....................................................................................................................................52
Table 8.6 - Verify Command Result Phase Table..........................................................................................................53
Table 8.7 - Format Fields..............................................................................................................................................54
Table 8.8 - Typical Values for Formatting......................................................................................................................55
Table 8.9 - Interrupt Identification..................................................................................................................................57
Table 8.10 - Drive Control Delays (ms) .........................................................................................................................58
Table 8.11 - Effects of WGATE and GAP Bits...............................................................................................................61
Table 9.1 - Addressing the Serial Port...........................................................................................................................63
Table 9.2 - Interrupt Control Table ................................................................................................................................67
Table 9.3 - Baud Rates Using 1.8462 MHz Clock for <= 38.4K; Using 1.8432MHz Clock for 115.2k; Using 3.6864MHz
Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k..........................................................................................73
Table 9.4 - Reset Function Table..................................................................................................................................74
Table 9.5 - Register Summary for an Individual UART Channel ..................................................................................75
Table 11.1 - DRVDEN1 MUXING.................................................................................................................................79
SMSC FDC37C672
Page 7
Rev. 10-29-03
PRELIMINARY DATASHEET
SMSC [ SMSC CORPORATION ]
