the next section.) Single byte wide transfers
are always possible with standard or PS/2 mode
using program control of the control signals.
FIFO. Also, an interrupt is generated
when serviceIntr is cleared to “0”
whenever there are readIntrThreshold or
more bytes in the FIFO.
Interrupts
3. When nErrIntrEn is 0 and nFault transitions
from high to low or when nErrIntrEn is set
from 1 to 0 and nFault is asserted.
The interrupts are enabled by serviceIntr in the
ecr register.
4. When ackIntEn is 1 and the nAck signal
transitions from a low to a high.
serviceIntr = 1 Disables the DMA and all of the
service interrupts.
serviceIntr = 0 Enables the selected interrupt
condition. If the interrupting
FIFO Operation
condition is valid, then the
The FIFO threshold is set in the chip
configuration registers. All data transfers to or
from the parallel port can proceed in DMA or
Programmed I/O (non-DMA) mode as indicated
by the selected mode. The FIFO is used by
selecting the Parallel Port FIFO mode or ECP
Parallel Port Mode. (FIFO test mode will be
addressed separately.) After a reset, the FIFO
is disabled. Each data byte is transferred by a
Programmed I/O cycle or PDRQ depending on
the selection of DMA or Programmed I/O mode.
interrupt
is
generated
immediately when this bit is
changed from a 1 to a 0. This
can occur during Programmed
I/O if the number of bytes
removed or added from/to the
FIFO does not cross the
threshold.
The interrupt generated is ISA friendly in that it
must pulse the interrupt line low, allowing for
interrupt sharing.
following the interrupt event, the interrupt line is
tri-stated so that other interrupts may assert.
After a brief pulse low
The following paragraphs detail the operation of
the FIFO flow control. In these descriptions,
<threshold> ranges from
1
to 16.
The
parameter FIFOTHR, which the user programs,
is one less and ranges from 0 to 15.
An interrupt is generated when:
1. For DMA transfers: When serviceIntr is 0,
dmaEn is 1 and the DMA TC is received.
A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases. The host must be very
responsive to the service request. This is the
desired case for use with a "fast" system.
2. For Programmed I/O:
a. When serviceIntr is 0, dmaEn is 0,
direction
writeIntrThreshold or more free bytes in
the FIFO. Also, an interrupt is
is
0
and
there
are
A high value of threshold (i.e. 12) is used with a
"sluggish" system by affording a long latency
period after a service request, but results in
more frequent service requests.
generated when serviceIntr is cleared to
0 whenever there are writeIntrThreshold
or more free bytes in the FIFO.
b. When serviceIntr is 0, dmaEn is 0,
direction
is
1
and
there
are
readIntrThreshold or more bytes in the
106
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