TQFP
PIN #
BUFFER
TYPE
O6
NAME
SYMBOL
DESCRIPTION
81,91 nData
nDTR1
Active low Data Terminal Ready outputs for the serial
port. Handshake output signal notifies modem that
the UART is ready to establish data communication
link. This signal can be programmed by writing to bit 0
of Modem Control Register (MCR). The hardware
reset will reset the nDTR signal to inactive mode
(high). nDTR is forced inactive during loop mode
operation.
Terminal
Ready
nDTR2
80,90 nClear to
Send
nCTS1
nCTS2
I
Active low Clear to Send inputs for the serial port.
Handshake signal which notifies the UART that the
modem is ready to receive data. The CPU can
monitor the status of nCTS signal by reading bit 4 of
Modem Status Register (MSR). A nCTS signal state
change from low to high after the last MSR read will
set MSR bit 0 to a 1. If bit 3 of the Interrupt Enable
Register is set, the interrupt is generated when nCTS
changes state. The nCTS signal has no effect on the
transmitter. Note: Bit 4 of MSR is the complement of
nCTS.
78,88 nData Set
Ready
nDSR1
nDSR2
I
I
Active low Data Set Ready inputs for the serial port.
Handshake signal which notifies the UART that the
modem is ready to establish the communication link.
The CPU can monitor the status of nDSR signal by
reading bit 5 of Modem Status Register (MSR).
A
nDSR signal state change from low to high after the
last MSR read will set MSR bit 1 to a 1. If bit 3 of
Interrupt Enable Register is set, the interrupt is
generated when nDSR changes state. Note: Bit 5 of
MSR is the complement of nDSR.
83,85 nData
Carrier
nDCD1
nDCD2
Active low Data Carrier Detect inputs for the serial
port. Handshake signal which notifies the UART that
carrier signal is detected by the modem. The CPU
can monitor the status of nDCD signal by reading bit 7
of Modem Status Register (MSR). A nDCD signal
state change from low to high after the last MSR read
will set MSR bit 3 to a 1. If bit 3 of Interrupt Enable
Register is set, the interrupt is generated when nDCD
Detect
changes state.
Note:
Bit 7 of MSR is the
complement of nDCD.
82,84 nRing
Indicator
nRI1
nRI2
I
Active low Ring Indicator inputs for the serial port.
Handshake signal which notifies the UART that the
telephone ring signal is detected by the modem. The
CPU can monitor the status of nRI signal by reading
bit 6 of Modem Status Register (MSR). A nRI signal
state change from low to high after the last MSR read
will set MSR bit 2 to a 1. If bit 3 of Interrupt Enable
Register is set, the interrupt is generated when nRI
(Note1)
changes state.
Note:
Bit 6 of MSR is the
complement of nRI.
TQFP
BUFFER
TYPE
PIN #
NAME
SYMBOL
DESCRIPTION
PARALLEL PORT INTERFACE (NOTE 2)
71
nPrinter
Select
nSLCTIN
(OD14/OP1 This active low output selects the printer. This is the
4)/OD12
complement of bit 3 of the Printer Control Register.
Refer to Parallel Port description for use of this pin in
ECP and EPP mode.
Input/FDC
nStep
Pulse
See FDC Pin definition.
(Note3)
nSTEP
SMSC DS – FDC37N769
Page 10 of 137
Rev. 12/21/2000
SMSC [ SMSC CORPORATION ]
