DOR RESET VS. DSR RESET (SOFTWARE RESET)
These two resets are functionally the same. Both will reset the FDC core, which affects drive status information and
the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires the host to manually clear it.
DOR reset has precedence over the DSR reset. The DOR reset is set automatically upon a pin reset. The user must
manually clear this reset bit in the DOR to exit the reset state.
DMA Transfers
DMA transfers are enabled with the Specify command and are initiated by the FDC by activating the FDRQ pin during
a data transfer command. The FIFO is enabled directly by asserting nDACK and addresses need not be valid.
Note that if the DMA controller (i.e. 8237A) is programmed to function in verify mode, a pseudo read is performed by
the FDC based only on nDACK. This mode is only available when the FDC has been configured into byte mode
(FIFO disabled) and is programmed to do a read. With the FIFO enabled, the FDC can perform the above operation
by using the new Verify command; no DMA operation is needed.
Controller Phases
For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and Result.
Each phase is described in the following sections.
COMMAND PHASE
After a reset, the FDC enters the command phase and is ready to accept a command from the host. For each of the
commands, a defined set of command code bytes and parameter bytes has to be written to the FDC before the
command phase is complete. (Refer to Table 33 for the command set descriptions). These bytes of data must be
transferred in the order prescribed.
Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM and DIO
must be equal to “1” and “0” respectively before command bytes may be written. RQM is set false by the FDC after
each write cycle until the received byte is processed. The FDC asserts RQM again to request each parameter byte of
the command unless an illegal command condition is detected. After the last parameter byte is received, RQM
remains “0” and the FDC automatically enters the next phase as defined by the command definition.
The FIFO is disabled during the command phase to provide for the proper handling of the “Invalid Command”
condition.
EXECUTION PHASE
All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or non-DMA mode
as indicated in the Specify command.
After a reset, the FIFO is disabled. Each data byte is transferred by an FINT or FDRQ depending on the DMA mode.
The Configure command can enable the FIFO and set the FIFO threshold value.
The following paragraphs detail the operation of the FIFO flow control. In these descriptions, <threshold> is defined
as the number of bytes available to the FDC when service is requested from the host and ranges from 1 to 16. The
parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing
of the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then the
transfer request goes inactive. The host must be very responsive to the service request. This is the desired case for
use with a “fast” system. A high value of threshold (i.e. 12) is used with a “sluggish” system by affording a long latency
period after a service request, but results in more frequent service requests.
SMSC DS – FDC37N3869
Page 33
Rev. 10/25/2000
SMSC [ SMSC CORPORATION ]
