Table 30 - Status Register 2
DESCRIPTION
Unused. This bit is always “0”.
Any one of the following:
BIT NO. SYMBOL
NAME
7
6
CM
Control
Mark
1. Read Data command - the FDC encountered a deleted data address
mark.
2. Read Deleted Data command - the FDC encountered a data address
mark.
5
4
DD
Data Error The FDC detected a CRC error in the data field.
in Data
Field
WC
Wrong
The track address from the sector ID field is different from the track address
maintained inside the FDC.
Cylinder
3
2
1
Unused. This bit is always “0”.
Unused. This bit is always “0”.
The track address from the sector ID field is different from the track address
maintained inside the FDC and is equal to FF hex, which indicates a bad
track with a hard error according to the IBM soft-sectored format.
BC
Bad
Cylinder
0
MD
Missing
Data
The FDC cannot detect a data address mark or a deleted data address
mark.
Address
Mark
Table 31 - Status Register 3
BIT NO. SYMBOL
NAME
DESCRIPTION
Unused. This bit is always “0”.
7
6
WP
Write
Indicates the status of the WP pin. The Write Protected bit also depends
upon the state of the Force Write Protect bits in the Force FDD Status
Change configuration register (see section
Protected
CR17 on page 109).
5
4
3
2
Unused. This bit is always “1”.
Indicates the status of the TRK0 pin.
Unused. This bit is always “1”.
Indicates the status of the HDSEL pin.
T0
Track 0
HD
Head
Address
1,0
DS1,0
Drive
Indicates the status of the DS1, DS0 pins.
Select
Reset
There are three sources of system reset on the FDC: the RESET pin of the FDC37N3869, a reset generated via a bit
in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All
resets take the FDC out of the power down state.
All operations are terminated upon a RESET, and the FDC enters an idle state. A reset while a disk write is in
progress will corrupt the data and CRC.
On exiting the reset state, various internal registers are cleared, including the Configure command information, and
the FDC waits for a new command. Drive polling will start unless disabled by a new Configure command.
RESET PIN (HARDWARE RESET)
The RESET pin is a global reset and clears all registers except those programmed by the Specify command. The
DOR reset bit is enabled and must be cleared by the host to exit the reset state.
SMSC DS – FDC37N3869
Page 32
Rev. 10/25/2000
SMSC [ SMSC CORPORATION ]
