Status Register Encoding
During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the
command just executed.
Table 28 - Status Register 0
BIT NO. SYMBOL
NAME
DESCRIPTION
7,6
IC
Interrupt
00 - Normal termination of command. The specified command was properly
Code
executed and completed without error.
01 - Abnormal termination of command. Command execution was started,
but was not successfully completed.
10 - Invalid command. The requested command could not be executed.
11 - Abnormal termination caused by Polling.
5
4
SE
EC
Seek End
The FDC completed a Seek, Relative Seek or Recalibrate command (used
during a Sense Interrupt Command).
Equipment The TRK0 pin failed to become a “1” after:
Check
1. 80 step pulses in the Recalibrate command.
2. The Relative Seek command caused the FDC to step outward beyond
Track 0.
3
2
Unused. This bit is always “0”.
The current head address.
H
Head
Address
1,0
DS1,0
Drive
The current selected drive.
Select
Table 29 - Status Register 1
DESCRIPTION
BIT NO. SYMBOL
NAME
7
EN
End of
The FDC tried to access a sector beyond the final sector of the track (255D).
Cylinder
Will be set if TC is not issued after Read or Write Data command.
6
5
Unused. This bit is always “0”.
DE
OR
Data Error The FDC detected a CRC error in either the ID field or the data field of a
sector.
4
Overrun/
Underrun
Becomes set if the FDC does not receive CPU or DMA service within the
required time interval, resulting in data overrun or underrun.
3
2
Unused. This bit is always “0”.
Any one of the following:
ND
No Data
1. Read Data, Read Deleted Data command - the FDC did not find the
specified sector.
2. Read ID command - the FDC cannot read the ID field without an error.
3. Read A Track command - the FDC cannot find the proper sector
sequence.
1
0
NW
MA
Not
WP pin became a “1” while the FDC is executing a Write Data, Write Deleted
Data, or Format A Track command.
Writable
Missing
Address
Mark
Any one of the following:
1. The FDC did not detect an ID address mark at the specified track after
encountering the index pulse from the IDX pin twice.
2. The FDC cannot detect a data address mark or a deleted data address
mark on the specified track.
SMSC DS – FDC37N3869
Page 31
Rev. 10/25/2000
SMSC [ SMSC CORPORATION ]
