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FDC37N769_07 参数 Datasheet PDF下载

FDC37N769_07图片预览
型号: FDC37N769_07
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V超级I / O控制器具有红外支持针对便携式应用 [3.3V Super I/O Controller with Infrared Support for Portable Applications]
分类和应用: 控制器便携式
文件页数/大小: 137 页 / 659 K
品牌: SMSC [ SMSC CORPORATION ]
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PIN DESCRIPTION  
BUFFER TYPE PER PIN  
Table 1 - DESCRIPTION OF PIN FUNCTIONS  
BUFFER  
TQFP  
PIN #  
NAME  
SYMBOL  
TYPE  
DESCRIPTION  
HOST PROCESSOR INTERFACE  
46-49 Data Bus 0- D0-D7  
IO12  
The data bus connection used by the host  
51-54  
7
microprocessor to transmit data to and from the chip.  
These pins are in a high-impedance state when not in  
the output mode.  
42  
43  
44  
nI/O Read  
nI/O Write  
nIOR  
nIOW  
AEN  
IS  
IS  
IS  
This active low signal is issued by the host micropro-  
cessor to indicate an I/O read operation.  
This active low signal is issued by the host micropro-  
cessor to indicate an I/O write operation.  
Active high Address Enable indicates DMA operations  
on the host data bus. Used internally to qualify  
appropriate address decodes.  
Address  
Enable  
26-32 Address  
39-41, Bus  
95  
A0-A10  
I
These host address bits determine the I/O address to  
be accessed during nIOR and nIOW cycles. These  
bits are latched internally by the leading edge of nIOR  
and nIOW. All internal address decodes use the full  
A0 to A10 address bits.  
19,50, DMA  
DRQ_A  
DRQ_B  
DRQ_C  
O12  
These active high outputs are the DMA request for  
byte transfers of data between the host and the chip.  
These signals are cleared on the last byte of the data  
transfer by the nDACK signal going low (or by nIOR  
going low if nDACK was already low as in demand  
mode).  
97  
Request  
A, B, C  
20,34, nDMA  
nDACK_A  
nDACK_B  
nDACK_C  
IS  
IS  
These are active low inputs acknowledging the  
request for a DMA transfer of data between the host  
and the chip. These inputs enable the DMA read or  
write internally.  
This signal indicates that DMA data transfer is  
complete. TC is only accepted when nDACK_x is  
low. In AT and PS/2 model 30 modes, TC is active  
high and in PS/2 mode, TC is active low.  
94  
Acknowl-  
edge  
A, B, C  
Terminal  
Count  
33  
TC  
17,  
Interrupt  
IRQ_A  
IRQ_C  
IRQ_D  
O12/OD12 Interrupt requests from a logical device or IRQIN are  
output on one of the IRQA-H signals. Refer to the  
configuration registers section for additional  
information.  
35-38, Request  
22  
A, C, D,  
E, F, and H IRQ_E  
IRQ_F  
If EPP or ECP Mode is enabled this output is pulsed  
low and released to allow sharing of interrupts.  
IRQ_H  
25  
55  
Chip Select nCS  
Input  
I
This active low input serves as an external decoder  
for address lines above A10.  
Reset  
RESET  
IS  
This active high signal resets the chip and must be  
valid for 500ns minimum. The effect on the internal  
registers is described in the appropriate section. The  
configuration registers are not affected by this reset.  
This pin is pulled low to extend the read/write  
command. IOCHRDY can used by the IRCC and by  
the Parallel Port in EPP mode.  
98  
I/O Channel IOCHRDY  
OD12  
Ready  
(Note4)  
FLOPPY DISK INTERFACE  
IS Raw serial bit stream from the disk drive, low active.  
Each falling edge represents a flux transition of the  
encoded data.  
O12/OD12 This active low high current driver allows current to  
flow through the write head. It becomes active just  
prior to writing to the diskette.  
14  
8
nRead Disk nRDATA  
Data  
nWrite  
Gate  
nWGATE  
SMSC DS – FDC37N769  
Page 8 of 137  
Rev. 02-16-07  
DATASHEET  
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