PIN DESCRIPTION
BUFFER TYPE PER PIN
TQFP
PIN #
46-49
51-54
42
43
44
26-32
39-41,
95
19,50,
97
Table 1 - DESCRIPTION OF PIN FUNCTIONS
BUFFER
NAME
SYMBOL
TYPE
DESCRIPTION
HOST PROCESSOR INTERFACE
Data Bus 0- D0-D7
IO12
The data bus connection used by the host
7
microprocessor to transmit data to and from the chip.
These pins are in a high-impedance state when not in
the output mode.
nI/O Read
nIOR
IS
This active low signal is issued by the host micropro-
cessor to indicate an I/O read operation.
nI/O Write
nIOW
IS
This active low signal is issued by the host micropro-
cessor to indicate an I/O write operation.
Address
AEN
IS
Active high Address Enable indicates DMA operations
Enable
on the host data bus. Used internally to qualify
appropriate address decodes.
Address
A0-A10
I
These host address bits determine the I/O address to
Bus
be accessed during nIOR and nIOW cycles. These
bits are latched internally by the leading edge of nIOR
and nIOW. All internal address decodes use the full
A0 to A10 address bits.
O12
These active high outputs are the DMA request for
DRQ_A
DMA
byte transfers of data between the host and the chip.
DRQ_B
Request
These signals are cleared on the last byte of the data
DRQ_C
A, B, C
transfer by the nDACK signal going low (or by nIOR
going low if nDACK was already low as in demand
mode).
IS
These are active low inputs acknowledging the
nDACK_A
nDMA
request for a DMA transfer of data between the host
nDACK_B
Acknowl-
and the chip. These inputs enable the DMA read or
nDACK_C
edge
write internally.
A, B, C
Terminal
TC
IS
This signal indicates that DMA data transfer is
Count
complete. TC is only accepted when nDACK_x is
low. In AT and PS/2 model 30 modes, TC is active
high and in PS/2 mode, TC is active low.
O12/OD12 Interrupt requests from a logical device or IRQIN are
IRQ_A
Interrupt
output on one of the IRQA-H signals. Refer to the
IRQ_C
Request
configuration registers section for additional
IRQ_D
A, C, D,
information.
E, F, and H IRQ_E
If EPP or ECP Mode is enabled this output is pulsed
IRQ_F
low and released to allow sharing of interrupts.
IRQ_H
Chip Select nCS
I
This active low input serves as an external decoder
Input
for address lines above A10.
Reset
RESET
IS
This active high signal resets the chip and must be
valid for 500ns minimum. The effect on the internal
registers is described in the appropriate section. The
configuration registers are not affected by this reset.
OD12
This pin is pulled low to extend the read/write
I/O Channel IOCHRDY
command. IOCHRDY can used by the IRCC and by
Ready
4
the Parallel Port in EPP mode.
(Note )
FLOPPY DISK INTERFACE
nRead Disk nRDATA
IS
Raw serial bit stream from the disk drive, low active.
Data
Each falling edge represents a flux transition of the
encoded data.
nWrite
nWGATE
O12/OD12 This active low high current driver allows current to
Gate
flow through the write head. It becomes active just
prior to writing to the diskette.
20,34,
94
33
17,
35-38,
22
25
55
98
14
8
SMSC DS – FDC37N769
Page 8 of 137
Rev. 02-16-07
DATASHEET
SMSC [ SMSC CORPORATION ]
