FIGURE 12B - EPP 1.9 DATA OR ADDRESS WRITE CYCLE TIMING
NAME
DESCRIPTION
nIOW Asserted to PDATA Valid
MIN
0
TYP
MAX
50
UNITS
ns
t1
t2
t3
t4
nWAIT Asserted to nWRITE Change (Note 1)
nWRITE to Command Asserted
60
5
185
35
ns
ns
nWAIT Deasserted to Command Deasserted
(Note 1)
60
190
ns
t5
t6
nWAIT Asserted to PDATA Invalid (Note 1)
Time Out
0
10
0
ns
ms
ns
ns
ns
ns
ns
12
t7
Command Deasserted to nWAIT Asserted
SDATA Valid to nIOW Asserted
nIOW Deasserted to DATA Invalid
nIOW Asserted to IOCHRDY Asserted
t8
10
0
t9
t10
t11
0
24
nWAIT Deasserted to IOCHRDY Deasserted
(Note 1)
60
160
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
IOCHRDY Deasserted to nIOW Deasserted
nIOW Asserted to nWRITE Asserted
nWAIT Asserted to Command Asserted (Note 1)
Command Asserted to nWAIT Deasserted
PDATA Valid to Command Asserted
Ax Valid to nIOW Asserted
10
0
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
70
210
10
60
0
10
40
10
40
60
0
nIOW Asserted to Ax Invalid
nIOW Deasserted to nIOW or nIOR Asserted
nWAIT Asserted to nWRITE Asserted (Note 1)
nWAIT Asserted to PDIR Low
185
PDIR Low to nWRITE Asserted
0
Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is
considered to have settled after it does not transition for a minimum of 50 nsec.
164
SMSC [ SMSC CORPORATION ]
