t15
AEN
t16
t3
t2
FDRQ,
PDRQ
t1
t4
nDACK
t12
t14
t11
t6
t5
t8
nIOR
or
nIOW
t10
t9
t7
DATA
(DO-D7)
DATA VALID
t13
TC
FIGURE 8A - DMA TIMING (SINGLE TRANSFER MODE)
NAME
t1
DESCRIPTION
nDACK Delay Time from FDRQ High
DRQ Reset Delay from nIOR or nIOW
FDRQ Reset Delay from nDACK Low
nDACK Width
MIN
TYP
MAX
UNITS
ns
0
t2
100
100
ns
t3
ns
t4
150
0
ns
t5
nIOR Delay from FDRQ High
nIOW Delay from FDRQ High
Data Access Time from nIOR Low
Data Set Up Time to nIOW High
Data to Float Delay from nIOR High
Data Hold Time from nIOW High
nDACK Set Up to nIOW/nIOR Low
nDACK Hold after nIOW/nIOR High
TC Pulse Width
ns
t6
0
ns
t7
100
60
ns
t8
40
10
10
5
ns
t9
ns
t10
t11
t12
t13
t14
t15
t16
ns
ns
10
60
40
10
ns
ns
AEN Set Up to nIOR/nIOW
ns
AEN Hold from nDACK
ns
TC Active to PDRQ Inactive
100
ns
158
SMSC [ SMSC CORPORATION ]
