Timing Diagrams For IRQSER Cycle
SERIAL IRQ
PCICLK = 33 MHz_IN pin
IRQSER = SIRQ pin
The FDC37M60x will support the serial interrupt
to transmit interrupt information to the host
system. The serial interrupt scheme adheres to
the Serial IRQ Specification for PCI Systems,
Version 6.0.
A) Start Frame timing with source sampled a low pulse on IRQ1
START FRAME
IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME
SL
or
H
R
T
S
R
T
S
R
T
S
R
T
H
PCICLK
START1
IRQSER
IRQ1 Host Controller
None
IRQ1
None
Drive Source
H=Host Control, R=Recovery, SL=Slave Control, T=Turn-Around, S=Sample
1) Start Frame pulse can be 4-8 clocks wide.
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