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FDC37C669_07 参数 Datasheet PDF下载

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型号: FDC37C669_07
PDF下载: 下载PDF文件 查看货源
内容描述: 98/99 PC兼容的超级I / O软盘控制器,红外支持 [PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support]
分类和应用: 控制器PC
文件页数/大小: 164 页 / 575 K
品牌: SMSC [ SMSC CORPORATION ]
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DESCRIPTION OF PIN FUNCTIONS  
BUFFER  
QFP/  
TQFP  
PIN NO.  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
82,92 nClear to Send  
nCTS1  
nCTS2  
I
Active low Clear to Send inputs for the serial  
port. Handshake signal which notifies the  
UART that the modem is ready to receive  
data. The CPU can monitor the status of  
nCTS signal by reading bit 4 of Modem  
Status Register (MSR). A nCTS signal state  
change from low to high after the last MSR  
read will set MSR bit 0 to a 1. If bit 3 of  
Interrupt Enable Register is set, the interrupt  
is generated when nCTS changes state.  
The nCTS signal has no effect on the  
transmitter. Note: Bit 4 of MSR is the  
complement of nCTS.  
80,90 nData Set Ready nDSR1  
nDSR2  
I
Active low Data Set Ready inputs for the  
serial port. Handshake signal which notifies  
the UART that the modem is ready to  
establish the communication link. The CPU  
can monitor the status of nDSR signal by  
reading bit 5 of Modem Status Register  
(MSR). A nDSR signal state change from  
low to high after the last MSR read will set  
MSR bit 1 to a 1. If bit 3 of Interrupt Enable  
Register is set, the interrupt is generated  
when nDSR changes state. Note: Bit 5 of  
MSR is the complement of nDSR.  
85,87 nData Carrier  
Detect  
nDCD1  
nDCD2  
I
Active low Data Carrier Detect inputs for the  
serial port. Handshake signal which notifies  
the UART that carrier signal is detected by  
the modem. The CPU can monitor the  
status of nDCD signal by reading bit 7 of  
Modem Status Register (MSR). A nDCD  
signal state change from low to high after  
the last MSR read will set MSR bit 3 to a 1.  
If bit 3 of Interrupt Enable Register is set,  
the interrupt is generated when nDCD  
changes state. Note: Bit 7 of MSR is the  
complement of nDCD.  
10