DESCRIPTION OF PIN FUNCTIONS
QFP/
TQFP
PIN NO.
NAME
Data Bus 0-7
SYMBOL
D0-D7
BUFFER
TYPE
DESCRIPTION
The data bus connection used by the host
microprocessor to transmit data to and from
the chip.
These pins are in a high-
impedance state when not in the output
mode.
This active low signal is issued by the host
microprocessor to indicate a read operation.
This active low signal is issued by the host
microprocessor to indicate a write operation.
Active high Address Enable indicates DMA
operations on the host data bus. Used
internally to qualify appropriate address
decodes.
These host address bits determine the I/O
address to be accessed during nIOR and
nIOW cycles.
These bits are latched
internally by the leading edge of nIOR and
nIOW. All internal address decodes use the
full A0 to A10 address bits.
This active high output is the DMA request
for byte transfers of data between the host
and the chip. This signal is cleared on the
last byte of the data transfer by the nDACK
signal going low (or by nIOR going low if
nDACK was already low as in demand
mode).
An active low input acknowledging the
request for a DMA transfer of data between
the host and the chip. This input enables
the DMA read or write internally.
This signal indicates to the chip that DMA
data transfer is complete.
TC is only
accepted when nDACK_x is low. In AT and
PS/2 model 30 modes, TC is active high
and in PS/2 mode, TC is active low.
HOST PROCESSOR INTERFACE
48-51
53-56
I/O24
44
45
46
nI/O Read
nI/O Write
Address Enable
nIOR
nIOW
AEN
I
I
I
28-34
41-43,
97
I/O Address
A0-A10
I
21,52,
99
DMA Request
A, B, C
DRQ_A
DRQ_B
DRQ_C
O24
22,36,
96
nDMA
Acknowledge
A, B, C
nDACK_A
nDACK_B
nDACK_C
TC
I
35
Terminal Count
I
6
SMSC [ SMSC CORPORATION ]
