DESCRIPTION OF PIN FUNCTIONS
BUFFER
QFP/
TQFP
PIN NO.
TYPE
NAME
SYMBOL
DESCRIPTION
63-66 Port Data
68-71
PD0-PD7
The bi-directional parallel data bus is used
to transfer information between CPU and
peripherals.
I/O24
100
IOCHRDY
IOCHRDY
In EPP mode, this pin is pulled low to
extend the read/write command. This pin
has an internal pull-up.
OD24P
IDE/ALT IR PINS
24
nIDE Enable
nIDEEN
IRQ_H
This active low signal is active when the IDE
(Note 1) is enabled and the I/O address is accessing
an IDE register.
O24P
Interrupt
Request H
The interrupt request from a logical device
or IRQIN may be output on the IRQH signal.
Refer to the configuration registers for more
information.
024
If EPP or ECP Mode is enabled, this output
is pulsed low, then released to allow sharing
of interrupts.
OD24
O24P
25
26
nIDE Chip
Select 0
nHDCS0
This is the Hard Disk Chip select
(Note 1) corresponding to the eight control block
addresses.
IRRX2
IRRX2
I
Alternate IR Receive input
nIDE Chip
Select 1
nHDCS1
This is the Hard Disk Chip select
O24P
(Note 1) corresponding to the alternate status
register.
IR Transmit 2
CLOCK 14
IRTX2
CLK14
Alternate IR transmit output
MISCELLANEOUS
ICLK The external connection to a single source
14.318 MHz clock.
O24P
20
13
SMSC [ SMSC CORPORATION ]
