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FDC37C669-MT 参数 Datasheet PDF下载

FDC37C669-MT图片预览
型号: FDC37C669-MT
PDF下载: 下载PDF文件 查看货源
内容描述: [Floppy Disk Drive, 0.25MBps, IDE Compatible, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100]
分类和应用: 数据传输PC驱动外围集成电路驱动器
文件页数/大小: 162 页 / 617 K
品牌: SMSC [ SMSC CORPORATION ]
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EXTENDED CAPABILITIES PARALLEL PORT  
PWord A port word; equal in size to the width of the  
ISA interface. For this implementation, PWord  
is always 8 bits.  
ECP provides a number of advantages, some of which  
are listed below. The individual features are explained in  
greater detail in the remainder of this section.  
1
0
A high level.  
A low level.  
High performance half-duplex forward and reverse  
channel  
These terms may be considered synonymous:  
Interlocked handshake, for fast reliable transfer  
Optional single byte RLE compression for improved  
throughput (64:1)  
Channel addressing for low-cost peripherals  
Maintains link and data layer separation  
Permits the use of active output drivers  
Permits the use of adaptive signal timing  
Peer-to-peer capability  
PeriphClk, nAck  
HostAck, nAutoFd  
PeriphAck, Busy  
nPeriphRequest, nFault  
nReverseRequest, nInit  
nAckReverse, PError  
Xflag, Select  
ECPMode, nSelectln  
HostClk, nStrobe  
Vocabulary  
The following terms are used in this document:  
Reference Document:  
assert When  
"true" state, when  
transitions to a "false" state.  
a
signal asserts it transitions to a  
IEEE 1284 Extended Capabilities Port Protocol and ISA  
a
signal deasserts it  
Interface Standard, Rev 1.09, Jan 7, 1993.  
document is available from Microsoft.  
This  
forward Host to Peripheral communication.  
reverse Peripheral to Host communication.  
The bit map of the Extended Parallel Port registers is:  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Note  
data  
PD7  
PD6  
PD5  
PD4  
PD3  
PD2  
PD1  
PD0  
ecpAFifo Addr/RLE  
Address or RLE field  
Select nFault  
ackIntEn SelectIn  
2
1
1
2
2
2
dsr  
nBusy  
0
nAck  
0
PError  
0
0
0
Direction  
dcr  
nInit  
autofd strobe  
cFifo  
ecpDFifo  
tFifo  
Parallel Port Data FIFO  
ECP Data FIFO  
Test FIFO  
cnfgA  
cnfgB  
ecr  
0
0
0
0
1
0
0
0
0
0
0
0
0
0
compress intrValue  
MODE  
nErrIntrEn  
serviceIntr  
dmaEn  
full  
empty  
Note 1: These registers are available in all modes.  
Note 2: All FIFOs use one common 16 byte FIFO.  
ISA IMPLEMENTATION STANDARD  
the Extended Capabilities Port (ECP). All ISA devices  
supporting ECP must meet the requirements contained in  
this section or the port will not be supported by Microsoft.  
This specification describes the standard ISA interface to  
95  
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