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FDC37C669-MT 参数 Datasheet PDF下载

FDC37C669-MT图片预览
型号: FDC37C669-MT
PDF下载: 下载PDF文件 查看货源
内容描述: [Floppy Disk Drive, 0.25MBps, IDE Compatible, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100]
分类和应用: 数据传输PC驱动外围集成电路驱动器
文件页数/大小: 162 页 / 617 K
品牌: SMSC [ SMSC CORPORATION ]
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Table 18 - Description of Command Symbols  
DESCRIPTION  
SYMBOL  
NCN  
NAME  
New Cylinder  
Number  
The desired cylinder number.  
ND  
Non-DMA Mode  
Flag  
When set to 1, indicates that the FDC is to operate in the non-DMA  
mode. In this mode, the host is interrupted for each data transfer.  
When set to 0, the FDC operates in DMA mode, interfacing to a DMA  
controller by means of the DRQ and nDACK signals.  
OW  
Overwrite  
The bits D0-D3 of the Perpendicular Mode Command can only be  
modified if OW is set to 1. OW id defined in the Lock command.  
PCN  
Present Cylinder  
Number  
The current position of the head at the completion of Sense Interrupt  
Status command.  
POLL  
PRETRK  
Polling Disable  
When set, the internal polling routine is disabled. When clear, polling  
is enabled.  
Precompensation Programmable from track 00 to FFH.  
Start Track  
Number  
R
Sector Address  
The sector number to be read or written. In multi-sector transfers,  
this parameter specifies the sector number of the first sector to be  
read or written.  
RCN  
SC  
Relative Cylinder  
Number  
Relative cylinder offset from present cylinder as used by the Relative  
Seek command.  
Number of Sectors The number of sectors per track to be initialized by the Format  
Per Track  
command. The number of sectors per track to be verified during a  
Verify command when EC is set.  
SK  
Skip Flag  
When set to 1, sectors containing a deleted data address mark will  
automatically be skipped during the execution of Read Data. If Read  
Deleted is executed, only sectors with a deleted address mark will be  
accessed. When set to "0", the sector is read or written the same as  
the read and write commands.  
SRT  
Step Rate Interval The time interval between step pulses issued by the FDC.  
Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at  
the 1 Mbit data rate. Refer to the SPECIFY command for actual  
delays.  
ST0  
Status 0  
Status 1  
Status 2  
Status 3  
Write Gate  
Registers within the FDC which store status information after a  
command has been executed. This status information is available to  
the host during the result phase after command execution.  
ST1  
ST2  
ST3  
WGATE  
Alters timing of WE to allow for pre-erase loads in perpendicular  
drives.  
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