Table 17 - Status Register 3
NAME
BIT NO.
SYMBOL
DESCRIPTION
7
6
Unused. This bit is always "0".
WP
Write
Indicates the status of the WP pin.
Protected
5
4
Unused. This bit is always "1".
Indicates the status of the TRK0 pin.
Unused. This bit is always "1".
T0
Track 0
3
2
HD
Head Address Indicates the status of the HDSEL pin.
1,0
DS1,0
Drive Select
Indicates the status of the DS1, DS0 pins.
RESET
DOR Reset vs. DSR Reset (Software Reset)
There are three sources of system reset on the FDC: The
RESET pin of the FDC37C669, a reset generated via a
bit in the DOR, and a reset generated via a bit in the
DSR. At power on, a Power On Reset initializes the
FDC. All resets take the FDC out of the power down
state.
These two resets are functionally the same. Both will
reset the FDC core, which affects drive status information
and the FIFO circuits. The DSR reset clears itself
automatically while the DOR reset requires the host to
manually clear it. DOR reset has precedence over the
DSR reset. The DOR reset is set automatically upon a
pin reset. The user must manually clear this reset bit in
the DOR to exit the reset state.
All operations are terminated upon a RESET, and the
FDC enters an idle state. A reset while a disk write is in
progress will corrupt the data and CRC.
MODES OF OPERATION
On exiting the reset state, various internal registers are
cleared, including the Configure command information,
and the FDC waits for a new command. Drive polling will
start unless disabled by a new Configure command.
The FDC has three modes of operation, PC/AT mode,
PS/2 mode and Model 30 mode. These are determined
by the state of the IDENT and MFM bits 6 and 5
respectively of configuration register 3.
RESET Pin (Hardware Reset)
PC/AT mode - (IDENT high, MFM a "don't care")
The RESET pin is a global reset and clears all registers
except those programmed by the Specify command. The
DOR reset bit is enabled and must be cleared by the host
to exit the reset state.
The PC/AT register set is enabled, the DMA enable bit of
the DOR becomes valid (FINTR and DRQ can be hi Z),
and TC and DENSEL become active high signals.
37
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