STATUS REGISTER B (SRB)
30 modes. The SRB can be accessed at any time when
in PS/2 mode. In the PC/AT mode the data bus pins D0 -
D7 are held in a high impedance state for a read of
address 3F1.
Address F1 READ ONLY
This register is read-only and monitors the state of
several disk interface pins, in PS/2 and Model
PS/2 Mode
7
1
6
1
5
4
3
2
1
0
DRIVE WDATA RDATA WGATE MOT
SEL0 TOGGLE TOGGLE
MOT
EN0
EN1
RESET
COND.
1
1
0
0
0
0
0
0
BIT 0 MOTOR ENABLE 0
BIT 4 WRITE DATA TOGGLE
Every inactive edge of the WDATA input causes this bit to
change state.
Active high status of the MTR0 disk interface output pin.
This bit is low after a hardware reset and unaffected by a
software reset.
BIT 5 DRIVE SELECT 0
BIT 1 MOTOR ENABLE 1
Reflects the status of the Drive Select 0 bit of the DOR
(address 3F2 bit 0). This bit is cleared after a hardware
reset, it is unaffected by a software reset.
Active high status of the MTR1 disk interface output pin.
This bit is low after a hardware reset and unaffected by a
software reset.
BIT 6 RESERVED
BIT 2 WRITE GATE
Always read as a logic "1".
Active high status of the WGATE disk interface output.
BIT 7 RESERVED
BIT 3 READ DATA TOGGLE
Always read as a logic "1".
Every inactive edge of the RDATA input causes this bit to
change state.
21
SMSC [ SMSC CORPORATION ]
