t18
t 9
AX
SD<7:0>
t17
t 8
t 6
t12
t19
nIOW
t10
t20
t11
IOCHRDY
nWRITE
t13
t 1
t 2
t 5
PD<7:0>
t16
t 3
t 4
nDATAST
nADDRSTB
t21
nWAIT
Parameter
nIOW Asserted t o PDATA Valid
Command Desssert ed to nWRI TE Change
nWRITE to Command
nI OW Deasserted to Command Deasserted
Command Deasserted to PDATA Invalid
Time Out
min
max
units
Notes
t1
t2
t3
t4
t5
t6
t8
t9
t10
t11
t12
t13
t16
t17
t18
t19
t20
t21
0
0
5
50
40
35
50
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
2
50
10
10
0
12
SDATA Valid t o nIOW Asserted
nIOW Deasserted to DATA Invalid
nIOW Asserted t o IOCHRDY Asserted
nWAIT Deassert ed to IOCHRDY Deasserted
IOCHRDY Deassert ed to nIOW Deasserted
nIOW Asserted to nWRITE Asserted
PDATA Valid to Command Asserted
Ax Valid to nIOW Assert ed
0
24
40
10
0
10
40
10
100
50
35
nIOW Deasserted to Ax Invalid
nIOW Deasserted to nIOW or nIOR Asserted
nWAIT Asserted to IOCHRDY Deasserted
Command Deasserted to nWAIT Deasserted
45
0
1. WRITE is controlled by clearing the PDIR bitto "0" inthe control register before
performing an EPPWrite.
2. This number is only valid if WAIT is active when nIOW goes active.
FIGURE 17 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE
154
SMSC [ SMSC CORPORATION ]
