t3
nDIR
t4
t1
t2
nSTEP
nDS0-3
nINDEX
nRDATA
t5
t6
t7
t8
nWDATA
nIOW
t9
t9
nDS0-1,
nM TR0-1
(AT Mode timing only)
Parameter
min
typ
max
units
t1
t2
t3
t4
t5
t6
t7
t8
t9
nDIR Set Up to nSTEP Low
nSTEPActive Time Low
nDIR Hold Time After nSTEP
nSTEP Cycle Time
nDS0-1 Hold Time from nSTEP Low
nINDEX Pulse Width
nRDATA Active Time Low
nWDATA Write Data Width Low
nDS0-1, MTR0-1 from End of nIOW
4
24
96
132
20
2
40
.5
25
X*
X*
X*
X*
X*
X*
ns
Y*
ns
*X specifies one MCLK period and Yspecifies one WCLK period.
MCLK = Controller Clock to FDC (See Table 6).
WCLK = 2 x Data Rate (See Table 6).
FIGURE 7 - DISK DRIVE TIMING
143