DESCRIPTION OF PIN FUNCTIONS
PIN NO.
48-51
53-56
NAME
Data Bus 0-7
SYMBOL
D0-D7
BUFFER
TYPE
I/O24
DESCRIPTION
The data bus connection used by the host
microprocessor to transmit data to and from
the FDC37C665GT. These pins are in a
high-impedance state when not in the output
mode.
This active low signal is issued by the host
microprocessor to indicate a read operation.
This active low signal is issued by the host
microprocessor to indicate a write operation.
Active high Address Enable indicates DMA
operations on the host data bus. Used
internally to qualify appropriate address
decodes.
These host address bits determine the I/O
address to be accessed during nIOR and
nIOW cycles.
These bits are latched
internally by the leading edge of nIOR and
nIOW.
This active high output is the DMA request
for byte transfers of data to the host. This
signal is cleared on the last byte of the data
transfer by the nDACK signal going low (or
by nIOR going low if nDACK was already
low as in demand mode).
An active low input acknowledging the
request for a DMA transfer of data. This
input enables the DMA read or write
internally.
This signal indicates to the FDC37C665GT
that data transfer is complete. TC is only
accepted when nDACK or nPDACK is low.
In AT and PS/2 model 30 modes, TC is
active high and in PS/2 mode, TC is active
low.
HOST PROCESSOR INTERFACE
44
45
46
nI/O Read
nI/O Write
Address Enable
nIOR
nIOW
AEN
I
I
I
28-34
41-43
I/O Address
A0-A9
I
52
FDC DMA
Request
FDRQ
O24
36
nDMA Acknowle- nDACK
dge
I
35
Terminal Count
TC
I
5
SMSC [ SMSC CORPORATION ]
