欢迎访问ic37.com |
会员登录 免费注册
发布采购

FDC37C665IRTQFP 参数 Datasheet PDF下载

FDC37C665IRTQFP图片预览
型号: FDC37C665IRTQFP
PDF下载: 下载PDF文件 查看货源
内容描述: [Multifunction Peripheral, CMOS, PQFP100, TQFP-100]
分类和应用: 驱动器存储微控制器和处理器次级存储控制器外围集成电路数据传输时钟
文件页数/大小: 152 页 / 616 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号FDC37C665IRTQFP的Datasheet PDF文件第8页浏览型号FDC37C665IRTQFP的Datasheet PDF文件第9页浏览型号FDC37C665IRTQFP的Datasheet PDF文件第10页浏览型号FDC37C665IRTQFP的Datasheet PDF文件第11页浏览型号FDC37C665IRTQFP的Datasheet PDF文件第13页浏览型号FDC37C665IRTQFP的Datasheet PDF文件第14页浏览型号FDC37C665IRTQFP的Datasheet PDF文件第15页浏览型号FDC37C665IRTQFP的Datasheet PDF文件第16页  
DESCRIPTION OF PIN FUNCTIONS  
BUFFER  
PIN NO.  
NAME  
SYMBOL  
TYPE  
DESCRIPTION  
82,92 nClear to Send  
nCTS1,  
nCTS2  
I
Active low Clear to Send inputs for primary  
and secondary serial ports. Handshake  
signal which notifies the UART that the  
modem is ready to receive data. The CPU  
can monitor the status of nCTS signal by  
reading bit 4 of Modem Status Register  
(MSR). A nCTS signal state change from  
low to high after the last MSR read will set  
MSR bit 0 to a 1. If bit 3 of Interrupt Enable  
Register is set, the interrupt is generated  
when nCTS changes state. The nCTS  
signal has no effect on the transmitter.  
Note: Bit 4 of MSR is the complement of  
nCTS.  
80,90 nData Set Ready nDSR1,  
nDSR2  
I
Active low Data Set Ready inputs for  
primary and secondary serial ports.  
Handshake signal which notifies the UART  
that the modem is ready to establish the  
communication link. The CPU can monitor  
the status of nDSR signal by reading bit 5 of  
Modem Status Register (MSR). A nDSR  
signal state change from low to high after  
the last MSR read will set MSR bit 1 to a 1.  
If bit 3 of Interrupt Enable Register is set,  
the interrupt is generated when nDSR  
changes state. Note: Bit 5 of MSR is the  
complement of nDSR.  
85,87 nData Carrier  
Detect  
nDCD1,  
nDCD2  
I
Active low Data Carrier Detect inputs for  
primary and secondary serial ports.  
Handshake signal which notifies the UART  
that carrier signal is detected by the  
modem. The CPU can monitor the status of  
nDCD signal by reading bit 7 of Modem  
Status Register (MSR). A nDCD signal  
state change from low to high after the last  
MSR read will set MSR bit 3 to a 1. If bit 3  
of Interrupt Enable Register is set, the  
interrupt is generated when nDCD changes  
state.  
Note:  
Bit 7 of MSR is the  
complement of nDCD.  
12