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FDC37C665IRQFP 参数 Datasheet PDF下载

FDC37C665IRQFP图片预览
型号: FDC37C665IRQFP
PDF下载: 下载PDF文件 查看货源
内容描述: [Multifunction Peripheral, CMOS, PQFP100, QFP-100]
分类和应用: 驱动器存储微控制器和处理器次级存储控制器外围集成电路数据传输时钟
文件页数/大小: 152 页 / 616 K
品牌: SMSC [ SMSC CORPORATION ]
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DESCRIPTION OF PIN FUNCTIONS  
BUFFER  
PIN NO.  
NAME  
SYMBOL  
TYPE  
DESCRIPTION  
84,86 nRing Indicator  
nRI1, nRI2  
I
Active low Ring Indicator input for primary  
and secondary serial ports. Handshake  
signal which notifies the UART that the  
telephone ring signal is detected by the  
modem. The CPU can monitor the status of  
nRI signal by reading bit 6 of Modem Status  
Register (MSR). A nRI signal state change  
from low to high after the last MSR read will  
set MSR bit 2 to a 1. If bit 3 of Interrupt  
Enable Register is set, the interrupt is  
generated when nRI changes state. Note:  
Bit 6 of MSR is the complement of nRI.  
94  
Drive 2  
nADRx  
DRV2  
I
In PS/2 mode, this input indicates whether a  
second drive is connected; DRV2 should be  
low if a second drive is connected. This  
status is reflected in a read of Status  
Register  
A.  
(Only  
available  
in  
FDC37C665GT.  
This pin must not be  
driven in the FDC37C666GT)  
nADRx  
O24  
Optional I/O port address decode output.  
Refer to Configuration registers CR3, CR8  
and CR9 for more information. Active low.  
(Available  
in  
FDC37C665GT  
and  
FDC37C666GT.) Defaults to tri-state after  
power-up. This pin has a 30ma internal pull-  
up.  
Parallel Port  
Interrupt  
Request 2  
PINTR2  
ECPEN  
O24  
This interrupt from the Parallel Port is  
enabled/disabled via bit 4 of the Parallel  
Port Control Register.  
Refer to  
configuration registers CR1 and CR3 for  
more information.  
I
FDC37C666GT (Adapter Mode): Enhanced  
Parallel Port mode select. Refer to  
FDC37C666GT hardware configuration for  
more information. Read and latched during  
reset active.  
PARALLEL PORT INTERFACE  
13