4. If nWAIT is asserted, IOCHRDY is
deasserted until the peripheral deasserts
nWAIT or a time-out occurs.
Read Sequence of Operation
1. The host sets PDIR bit in the control register
to a logic "1". This deasserts nWRITE and tri-
states the PData bus.
2. The host selects an EPP register and drives
nIOR active.
3. Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus is tri-stated, PDIR is
set and the nWRITE signal is valid.
5. The Peripheral drives PData bus valid.
6. The Peripheral deasserts nWAIT, indicating
that PData is valid and the chip may begin the
termination phase of the cycle.
7. When the host deasserts nIOR the chip
deasserts nDATASTB or nADDRSTRB.
8. Peripheral tri-states the PData bus.
9. Chip may modify nWRITE, PDIR and
nPDATA in preparation of the next cycle.
94
SMSC [ SMSC CORPORATION ]
