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FDC37B78X_07 参数 Datasheet PDF下载

FDC37B78X_07图片预览
型号: FDC37B78X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 超级I / O控制器,支持ACPI ,实时时钟和消费性红外端口 [Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR]
分类和应用: 控制器时钟
文件页数/大小: 249 页 / 865 K
品牌: SMSC [ SMSC CORPORATION ]
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Sense Interrupt Status command is issued after  
the Seek command to terminate it and to provide  
verification of the head position (PCN). The H bit  
(Head Address) in ST0 will always return to a "0".  
When exiting POWERDOWN mode, the FDC  
clears the PCN value and the status information to  
The Seek, Relative Seek, and Recalibrate  
commands have no result phase. The Sense  
Interrupt Status command must be issued  
immediately after these commands to terminate  
them and to provide verification of the head  
position (PCN). The H (Head Address) bit in ST0  
will always return a "0". If a Sense Interrupt Status  
is not issued, the drive will continue to be BUSY  
and may affect the operation of the next  
command.  
zero.  
Prior to issuing the POWERDOWN  
command, it is highly recommended that the user  
service all pending interrupts through the Sense  
Interrupt Status command.  
Sense Interrupt Status  
Sense Drive Status  
An interrupt signal on FINT pin is generated by the  
FDC for one of the following reasons:  
Sense Drive Status obtains drive status  
information. It has not execution phase and goes  
directly to the result phase from the command  
phase. Status Register 3 contains the drive status  
information.  
1. Upon entering the Result Phase of:  
a. Read Data command  
b. Read A Track command  
c. Read ID command  
Specify  
d. Read Deleted Data command  
e. Write Data command  
f. Format A Track command  
g. Write Deleted Data command  
h. Verify command  
The Specify command sets the initial values for  
each of the three internal times. The HUT (Head  
Unload Time) defines the time from the end of the  
execution phase of one of the read/write  
commands to the head unload state. The SRT  
(Step Rate Time) defines the time interval between  
adjacent step pulses. Note that the spacing  
between the first and second step pulses may be  
shorter than the remaining step pulses. The HLT  
(Head Load Time) defines the time between when  
the Head Load signal goes high and the read/write  
operation starts. The values change with the data  
rate speed selection and are documented in  
TABLE 31. The values are the same for MFM  
and FM.  
2. End of Seek, Relative Seek, or Recalibrate  
command  
3. FDC requires a data transfer during the  
execution phase in the non-DMA mode  
The Sense Interrupt Status command resets the  
interrupt signal and, via the IC code and SE bit of  
Status Register 0, identifies the cause of the  
interrupt.  
TABLE 30 - INTERRUPT IDENTIFICATION  
SE  
IC  
INTERRUPT DUE TO  
0
1
11  
00  
Polling  
TABLE 31 - DRIVE CONTROL DELAYS (MS)  
Normal termination of Seek  
or Recalibrate command  
Abnormal termination of  
Seek or Recalibrate  
command  
1
01  
HUT  
SRT  
500K 300K 250K  
2M  
1M  
500K 300K 250K  
2M  
1M  
0
1
64  
4
128  
8
256  
16  
426  
26.7  
512  
32  
4
3.75  
8
7.5  
16  
15  
26.7  
25  
32  
30  
65  
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