CLOCK TIMING
t2
t2
CLOCKI
FIGURE 16 - INPUT CLOCK TIMING
TABLE 95 - INPUT CLOCK TIMING
NAME
DESCRIPTION
MIN
TYP
70
MAX
UNITS
ns
t1
t2
t1
t2
Clock Cycle Time for 14.318MHZ
Clock High Time/Low Time for 14.318MHz
Clock Cycle Time for 32KHZ
35
ns
31.25
16.53
μs
Clock High Time/Low Time for 32KHz
Clock Rise Time/Fall Time (not shown)
μs
5
ns
FIGURE 17 - RESET TIMING
t4
RESET_DRV
TABLE 96 - RESET TIMING
NAME
DESCRIPTION
MIN
1.5
TYP MAX
UNITS
t4
RESET width (Note 1)
μs
Note 1: The RESET width is dependent upon the processor clock. The RESET must be active while
the clock is running and stable.
232